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| INTEGRATED CIRCUITS DATA SHEET SAA7113H 9-bit video input processor Product specification File under Integrated Circuits, IC22 1999 Jul 01 Philips Semiconductors Product specification 9-bit video input processor CONTENTS 1 2 3 4 5 6 7 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 9 9.1 9.2 10 11 12 13 14 15 15.1 15.2 16 17 18 18.1 18.2 18.3 18.4 18.5 19 20 21 FEATURES APPLICATIONS GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Analog input processing Analog control circuits Chrominance processing Luminance processing Synchronization Clock generation circuit Power-on reset and CE input Multi-standard VBI data slicer VBI-raw data bypass Digital output port VPO7 to VPO0 RTCO output RTS0, RTS1 terminals BOUNDARY SCAN TEST Initialization of boundary scan circuit Device identification codes LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS TIMING DIAGRAMS APPLICATION INFORMATION I2C-BUS DESCRIPTION I2C-bus format I2C-bus detail I2C-BUS START SET-UP PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS 2 SAA7113H 1999 Jul 01 Philips Semiconductors Product specification 9-bit video input processor 1 FEATURES SAA7113H * Four analog inputs, internal analog source selectors, e.g. 4 x CVBS or 2 x Y/C or (1 x Y/C and 2 x CVBS) * Two analog preprocessing channels in differential CMOS style for best S/N-performance * Fully programmable static gain or automatic gain control for the selected CVBS or Y/C channel * Switchable white peak control * Two built-in analog anti-aliasing filters * Two 9-bit video CMOS Analog-to-Digital Converters (ADCs), digitized CVBS or Y/C-signals are available on the VPO-port via I2C-bus control * On-chip clock generator * Line-locked system clock frequencies * Digital PLL for horizontal sync processing and clock generation, horizontal and vertical sync detection * Requires only one crystal (24.576 MHz) for all standards * Automatic detection of 50 and 60 Hz field frequency, and automatic switching between PAL and NTSC standards * Luminance and chrominance signal processing for PAL BGHI, PAL N, combination PAL N, PAL M, NTSC M, NTSC N, NTSC 4.43, NTSC-Japan and SECAM * User programmable luminance peaking or aperture correction * Cross-colour reduction for NTSC by chrominance comb filtering * PAL delay line for correcting PAL phase errors * Brightness Contrast Saturation (BCS) and hue control on-chip * Real-time status information output (RTCO) * Two multi functional real-time output pins controlled by I2C-bus * Multi-standard VBI-data slicer decoding World Standard Teletext (WST), North-American Broadcast Text System (NABTS), closed caption, Wide Screen Signalling (WSS), Video Programming System (VPS), Vertical Interval Time Code (VITC) variants (EBU/SMPTE) etc. * Standard ITU 656 YUV 4 : 2 : 2 format (8-bit) on VPO output bus * Enhanced ITU 656 output format on VPO output bus containing: - active video - raw CVBS data for INTERCAST applications (27 MHz data rate) - decoded VBI data * Boundary scan test circuit complies with the "IEEE Std. 1149.b1 - 1994" (ID-Code = 1 7113 02B) * I2C-bus controlled (full read-back ability by an external controller, bit rate up to 400 kbits/s) * Low power (<0.5 W), low voltage (3.3 V), small package (QFP44) * Power saving mode by chip enable input * 5 V tolerant digital I/O ports * Detection of copy protected input signals according to the macrovision standard. Can be used to prevent unauthorized recording of pay-TV or video tape signals. 2 APPLICATIONS * Notebook (low power consumption) * PCMCIA card application * AGP based graphics cards * Image processing * Video phone applications * Intercast and PC teletext applications * Security applications. 1999 Jul 01 3 Philips Semiconductors Product specification 9-bit video input processor 3 GENERAL DESCRIPTION SAA7113H The integrated high performance multi-standard data slicer supports several VBI data standards: * Teletext [WST (World Standard Teletext), CCST (Chinese teletext)] (625 lines) * Teletext [US-WST, NABTS (North-American Broadcast Text System) and MOJI (Japanese teletext)] (525 lines) * Closed caption [Europe, US (line 21)] * Wide Screen Signalling (WSS) * Video Programming Signal (VPS) * Time codes (VITC EBU/SMPTE) * HIGH-speed VBI data bypass for intercast application. The 9-bit video input processor is a combination of a two-channel analog preprocessing circuit including source selection, anti-aliasing filter and ADC, an automatic clamp and gain control, a Clock Generation Circuit (CGC), a digital multi-standard decoder (PAL BGHI, PAL M, PAL N, combination PAL N, NTSC M, NTSC-Japan, NTSC N and SECAM), a brightness, contrast and saturation control circuit, a multi-standard VBI data slicer and a 27 MHz VBI data bypass; see Fig.1. The pure 3.3 V (5 V compatible) CMOS circuit SAA7113H, analog front-end and digital video decoder, is a highly integrated circuit for desktop video applications. The decoder is based on the principle of line-locked clock decoding and is able to decode the colour of PAL, SECAM and NTSC signals into CCIR-601 compatible colour component values. The SAA7113H accepts as analog inputs CVBS or S-video (Y/C) from TV or VTR sources. The circuit is I2C-bus controlled. 4 QUICK REFERENCE DATA SYMBOL VDDD VDDA Tamb PA+D 5 PARAMETER digital supply voltage analog supply voltage operating ambient temperature analog and digital power dissipation MIN. 3.0 3.1 0 - 3.3 3.3 25 0.4 TYP. 3.6 3.5 70 - MAX. V V C W UNIT ORDERING INFORMATION TYPE NUMBER PACKAGE NAME DESCRIPTION VERSION SOT307-2 SAA7113H QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm 1999 Jul 01 4 Philips Semiconductors Product specification 9-bit video input processor 6 BLOCK DIAGRAM SAA7113H handbook, full pagewidth MULTI-STANDARD DATA SLICER 4 5 7 9 43 44 1 AD2 AD1 6 CON ANALOG PROCESSING CONTROL Y Y/CVBS LUMINANCE CIRCUIT I2C-BUS CONTROL I2C-BUS INTERFACE 23 SDA 24 SCL ANALOG PROCESSING AND ANALOG-TODIGITAL CONVERSION C/CVBS AI11 AI1D AI12 AOUT AI21 AI2D AI22 AGND VBI DATA BYPASS UPSAMPLING FILTER bypass UV Y OUTPUT FORMATTER 12 to 15, 19 to 22 VPO7 to VPO0 CHROMINANCE CIRCUIT AND BRIGHTNESS CONTRAST SATURATION CONTROL SAA7113H VSSA1 VSSA2 VDDA1 VDDA2 TDI TCK TMS TRST TDO 2 41 3 42 38 37 39 8 36 Y TEST CONTROL BLOCK FOR BOUNDARY SCAN TEST AND SCAN TEST 18 29 33 34 16 28 CLOCKS SYNCHRONIZATION CIRCUIT LFCO CLOCK GENERATION CIRCUIT POWER-ON CONTROL 10 11 40 31 32 XTAL XTALI 17 LLC 30 35 26 27 25 MHB323 VDDDE1 VDDDA VSSDE1 VSSDA RTS0 RTS1 RTCO VDDA0 VSSA0 CE VDDDI VDDDE2 VSSDI VSSDE2 Fig.1 Block diagram. 1999 Jul 01 5 Philips Semiconductors Product specification 9-bit video input processor 7 PINNING PIN 1 2 3 4 5 6 7 8 9 10 11 12 to 15 I/O/P I P P I I P I I O P P O analog input 22 ground for analog supply voltage channel 1 positive supply voltage for analog channel 1 (+3.3 V) analog input 11 DESCRIPTION SAA7113H SYMBOL AI22 VSSA1 VDDA1 AI11 AI1D AGND AI12 TRST AOUT VDDA0 VSSA0 VPO7 to VPO4 differential analog input for AI11 and AI12; has to be connected to ground via a capacitor; see application diagram of Fig.31 analog signal ground connection analog input 12 test reset input (active LOW), for boundary scan test; notes 1, 2 and 3 analog test output; for testing the analog input channels, 75 termination possible positive supply voltage (+3.3 V) for internal Clock Generation Circuit (CGC) ground for internal clock generation circuit digital VPO-bus output signal; higher bits of the 8-bit output bus. The output data types of the VPO-bus are controlled via I2C-bus registers LCR2 to LCR24; see Table 4. If I2C-bus bit VIPB = 1, the higher bits of the digitized input signal are connected to these outputs, configured by the I2C-bus control signals MODE3 to MODE0 ground 1 or digital supply voltage input E (external pad supply) line-locked system clock output (27 MHz) digital supply voltage E1 (external pad supply 1; +3.3 V) digital VPO-bus output signal; lower bits of the 8-bit output bus. The output data types of the VPO-bus are controlled via I2C-bus registers LCR2 to LCR24; see Table 4. If I2C-bus bit VIPB = 1, the lower bits of the digitized input signal are connected to these outputs, configured by the I2C-bus control signals MODE3 to MODE0 serial data input/output (I2C-bus) 5 V-compatible serial clock input (I2C-bus) 5 V-compatible real-time control output: contains information about actual system clock frequency, field rate, odd/even sequence, decoder status, subcarrier frequency and phase and PAL sequence (see external document "RTC Functional Description", available on request); the RTCO pin is enabled via I2C-bus bit OERT; this pin is also used as an input pin for test purposes and has an internal pull-down resistor; do not connect any pull-up resistor to this pin real-time signal output 0: multi functional output, controlled by I2C-bus bits RTSE03 to RTSE00; see Table 49. RTS0 is strapped during power-on or CE driven reset, defines which I2C-bus slave address is used; 0 = 48H for write, 49H for read, external pull-down resistor of 3.3 k is needed; 1 = 4AH for write, 4BH for read, default slave address (default, internal pull-up) real-time signal I/O terminal 1: multi functional output, controlled by I2C-bus bit RTSE13 to RTSE10; see Table 50 ground for internal digital core supply internal core supply (+3.3 V) digital ground for internal crystal oscillator second terminal of crystal oscillator; not connected if external clock signal is used VSSDE1 LLC VDDDE1 VPO3 to VPO0 16 17 18 19 to 22 P O P O SDA SCL RTCO 23 24 25 I/O I (I/)O RTS0 26 (I/)O RTS1 VSSDI VDDDI VSSDA XTAL 27 28 29 30 31 I/O P P P O 1999 Jul 01 6 Philips Semiconductors Product specification 9-bit video input processor SAA7113H SYMBOL XTALI VDDDA VDDDE2 VSSDE2 TDO TCK TDI TMS CE VSSA2 VDDA2 AI21 AI2D Notes PIN 32 33 34 35 36 37 38 39 40 41 42 43 44 I/O/P I P P P O I I I I P P I I DESCRIPTION input terminal for crystal oscillator or connection of external oscillator with CMOS compatible square wave clock signal digital positive supply voltage for internal crystal oscillator (+3.3 V) digital supply voltage E2 (external pad supply 2; +3.3 V) ground 2 for digital supply voltage input E (external pad supply) test data output for boundary scan test; note 3 test clock for boundary scan test; note 3 test data input for boundary scan test; note 3 test mode select input for boundary scan test or scan test; note 3 chip enable, `sleep mode' with low power consumption if connected to ground (internal pull-up); internal reset sequence is generated when released ground for analog supply voltage channel 2 positive supply voltage for analog channel 2 (+3.3 V) analog input 21 differential analog input for AI21 and AI22; has to be connected to ground via a capacitor; see application diagram of Fig.31 1. For board design without boundary scan implementation connect the TRST pin to ground. 2. This pin provides easy initialization of BST circuit. TRST can be used to force the Test Access Port (TAP) controller to the TEST_LOGIC_RESET state (normal operation) at once. 3. In accordance with the IEEE1149.1 standard the pads TDI, TMS and TRST are input pads with an internal pull-up transistor and TDO is a 3-state output pad. 1999 Jul 01 7 Philips Semiconductors Product specification 9-bit video input processor SAA7113H 42 VDDA2 41 VSSA2 handbook, full pagewidth 34 VDDDE2 35 VSSDE2 44 AI2D 39 TMS 36 TDO 43 AI21 37 TCK 38 TDI 40 CE AI22 1 VSSA1 2 VDDA1 3 AI11 4 AI1D 5 AGND 6 AI12 7 TRST 8 AOUT 9 VDDA0 10 VSSA0 11 33 VDDDA 32 XTALI 31 XTAL 30 VSSDA 29 VDDDI SAA7113H 28 VSSDI 27 RTS1 26 RTS0 25 RTCO 24 SCL 23 SDA VPO1 21 VSSDE1 16 VDDDE1 18 VPO0 22 VPO7 12 VPO6 13 VPO5 14 VPO4 15 LLC 17 VPO3 19 VPO2 20 MHB324 Fig.2 Pin configuration. 1999 Jul 01 8 Philips Semiconductors Product specification 9-bit video input processor 8 8.1 FUNCTIONAL DESCRIPTION Analog input processing 8.2 Analog control circuits SAA7113H The SAA7113H offers four analog signal inputs, two analog main channels with source switch, clamp circuit, analog amplifier, anti-alias filter and video 9-bit CMOS ADC; see Fig.6. The anti-alias filters are adapted to the line-locked clock frequency via a filter control circuit. The characteristics are shown in Fig.3. During the vertical blanking period, gain and clamping control are frozen. MGD138 handbook, full pagewidth 6 V (dB) 0 -6 -12 -18 -24 -30 -36 -42 0 2 4 6 8 10 12 f (MHz) 14 Fig.3 Anti-alias filter. 8.2.1 CLAMPING The clamp control circuit controls the correct clamping of the analog input signals. The coupling capacitor is also used to store and filter the clamping voltage. An internal digital clamp comparator generates the information with respect to clamp-up or clamp-down. The clamping levels for the two ADC channels are fixed for luminance (120) and chrominance (256). Clamping time in normal use is set with the HCL pulse at the back porch of the video signal. 8.2.2 GAIN CONTROL amplitude, matched to the ADCs input voltage range. The AGC active time is the sync bottom of the video signal. Signal (white) peak control limits the gain at signal overshoots. The flow charts (see Figs 7 and 8) show more details of the AGC. The influence of supply voltage variation within the specified range is automatically eliminated by clamp and automatic gain control. The gain control circuit receives (via the I2C-bus) the static gain levels for the two analog amplifiers or controls one of these amplifiers automatically via a built-in Automatic Gain Control (AGC) as part of the Analog Input Control (AICO). The AGC (automatic gain control for luminance) is used to amplify a CVBS or Y signal to the required signal 1999 Jul 01 9 Philips Semiconductors Product specification 9-bit video input processor SAA7113H handbook, halfpage TV line analog line blanking handbook, halfpage 255 analog input level +3 dB maximum controlled ADC input level GAIN 60 1 CLAMP 0 dB (1 V (p-p) 18/56 ) -6 dB range 9 dB 0 dB HCL HSY MGL065 minimum MHB325 Fig.4 Analog line with clamp (HCL) and gain range (HSY). Fig.5 Automatic gain range. 1999 Jul 01 10 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... ndbook, full pagewidth 1999 Jul 01 VSSA1 VSSA2 AI22 AI2D AI21 VDDA1 VDDA2 AI12 AI1D AI11 2 41 1 44 43 3 42 7 5 4 SOURCE SWITCH CLAMP CIRCUIT ANALOG AMPLIFIER DAC9 SOURCE SWITCH CLAMP CIRCUIT ANALOG AMPLIFIER DAC9 Philips Semiconductors 9-bit video input processor TEST SELECTOR AND BUFFER AOSL (1 : 0) 9 AOUT ANTI-ALIAS FILTER BYPASS SWITCH ADC2 FUSE (1 : 0) ANTI-ALIAS FILTER BYPASS SWITCH ADC1 FUSE (1 : 0) 11 MODE CONTROL CLAMP CONTROL GAIN CONTROL ANTI-ALIAS CONTROL VERTICAL BLANKING CONTROL MODE 3 MODE 2 MODE 1 MODE 0 HCL GLIMB HSY GLIMT WIPA SLTCA HOLDG GAFIX WPOFF GUDL0-GUDL2 GAI20-GAI28 GAI10-GAI18 HLNRS UPTCV VBSL VBLNK SVREF 9 9 ANALOG CONTROL AGND 6 CROSS MULTIPLEXER Product specification SAA7113H MHB326 LUM CHR AD2BYP AD1BYP Fig.6 Analog input processing using the SAA7113H as differential front-end with 9-bit ADC. Philips Semiconductors Product specification 9-bit video input processor SAA7113H handbook, full pagewidth ANALOG INPUT AMPLIFIER ANTI-ALIAS FILTER ADC 9 LUMA/CHROMA DECODER gain DAC 9 NO ACTION 1 VBLK 1 0 0 HOLDG 1 X 1 0 0 HSY 0 1 >254 1 1 0 1 0 0 <4 <1 >254 X=0 1 >248 0 X=1 +1/F STOP +1/L -1/LLC2 +1/LLC2 -1/LLC2 +/- 0 GAIN ACCUMULATOR (18 BITS) ACTUAL GAIN VALUE 9-BIT (AGV) [-6/+6 dB] 1 0 X 1 HSY 1 0 0 Y AGV UPDATE GAIN VALUE 9-BIT FGV MHB327 X = system variable; Y = (IAGV - FGVI) > GUDL; VBLK = vertical blanking pulse; HSY = horizontal sync pulse; AGV = actual gain value; FGV = frozen gain value. Fig.7 Gain flow chart. 1999 Jul 01 12 Philips Semiconductors Product specification 9-bit video input processor SAA7113H handbook, full pagewidth ANALOG INPUT ADC NO BLANKING ACTIVE 1 VBLK 0 <- CLAMP GAIN -> 1 HCL 0 1 HSY 0 1 CLL 0 0 SBOT 1 1 WIPE 0 + CLAMP - CLAMP NO CLAMP + GAIN - GAIN fast - GAIN slow + GAIN MGC647 WIPE = white peak level (254); SBOT = sync bottom level (1); CLL = clamp level [60 Y (128 C)]; HSY = horizontal sync pulse; HCL = horizontal clamp pulse. Fig.8 Clamp and gain flow. 8.3 Chrominance processing * Luminance contrast and brightness * Limiting YUV to the values 1 (minimum) and 254 (maximum) to fulfil CCIR-601 requirements. The SECAM-processing contains the following blocks: * Baseband `bell' filters to reconstruct the amplitude and phase equalized 0 and 90 FM signals * Phase demodulator and differentiator (FM-demodulation) * De-emphasis filter to compensate the pre-emphasized input signal, including frequency offset compensation (DB or DR white carrier values are subtracted from the signal, controlled by the SECAM switch signal). The burst processing block provides the feedback loop of the chrominance PLL and contains: * Burst gate accumulator * Colour identification and killer * Comparison nominal/actual burst amplitude (PAL/NTSC standards only) The 9-bit chrominance signal is fed to the multiplication inputs of a quadrature demodulator, where two subcarrier signals from the local oscillator DTO1 are applied (0 and 90 phase relationship to the demodulator axis). The frequency is dependent on the present colour standard. The output signals of the multipliers are low-pass filtered (four programmable characteristics) to achieve the desired bandwidth for the colour difference signals (PAL, NTSC) or the 0 and 90 FM signals (SECAM). The colour difference signals are fed to the Brightness/Contrast/Saturation block (BCS), which includes the following five functions: * AGC (automatic gain control for chrominance PAL and NTSC) * Chrominance amplitude matching (different gain factors for (R - Y) and (B - Y) to achieve CCIR-601 levels CR and CB for all standards) * Chrominance saturation control 1999 Jul 01 13 Philips Semiconductors Product specification 9-bit video input processor * Loop filter chrominance gain control (PAL/NTSC standards only) * Loop filter chrominance PLL (only active for PAL/NTSC standards) * PAL/SECAM sequence detection, H/2-switch generation * Increment generation for DTO1 with divider to generate stable subcarrier for non-standard signals. The chrominance comb filter block eliminates crosstalk between the chrominance channels in accordance with the PAL standard requirements. SAA7113H For NTSC colour standards the chrominance comb filter can be used to eliminate crosstalk from luminance to chrominance (cross-colour) for vertical structures. The comb filter can be switched off if desired. The embedded line delay is also used for SECAM recombination (cross-over switches). The resulting signals are fed to the variable Y-delay compensation and the output interface, which contains the VPO output formatter and the output control logic, see Fig.10. MGD147 handbook, full pagewidth V 6 0 (dB) -6 -12 -18 -24 -30 -36 -42 -48 -54 (4) (1) (3) (2) (1) (2) (3) (4) 0 0.54 1.08 1.62 2,16 f 2.7 (MHz) Transfer characteristics of the chrominance low-pass dependent on CHBW[1 : 0] settings. (1) CHBW[1 : 0] = 00. (2) CHBW[1 : 0] = 01. (3) CHBW[1 : 0] = 10. (4) CHBW[1 : 0] = 11. Fig.9 Chrominance filter. 1999 Jul 01 14 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... ndbook, full pagewidth 1999 Jul 01 LUM CHR TRST TCK TDI TMS TDO 8 37 38 39 36 SUBCARRIER GENERATION PHASE DEMODULATOR SUBCARRIER INCREMENT GENERATION AND DIVIDER AMPLITUDE DETECTOR BURST GATE ACCUMULATOR LOOP FILTER TEST CONTROL BLOCK QUADRATURE DEMODULATOR LOW-PASS CHBW0 CHBW1 RESET 18 29 33 34 CSTD 1 CSTD 0 INCS VBI DATA BYPASS UPSAMPLING FILTER FCTC CODE POWER-ON CONTROL VDDDE1 VDDDI VDDDA VDDDE2 HUEC Philips Semiconductors 9-bit video input processor AD2BYP AD1BYP SECAM PROCESSING sequential UV signals LEVEL ADJUSTMENT, BRIGHTNESS, CONTRAST, AND SATURATION CONTROL Y UV OUTPUT FORMATTER AND INTERFACE 12, 13, 14, 15, 19, 20, 21, 22 VPO7 to VPO0 GAIN CONTROL AND Y-DELAY COMPENSATION UV COMB FILTERS SECAM RECOMBINATION 15 CE CLOCKS VSSDE1 VSSDI VSSDA VSSDE2 16 28 30 35 BRIG CONT SATN DCCF fH/2 switch signal OFTS0 GPSW (1 : 0) RTSE1 (7 : 0) OFTS1 RTSE0 (7 : 0) OEYC OEHV VIPB VRLN COLO VSTA (8 : 0) VSTO (8 : 0) 25 RTCO DATA SLICER INPUT MULTI-STANDARD DATA SLICER MULTI-STANDARD DATA SLICER INTERFACING MHB328 LUM Y Product specification SAA7113H Fig.10 Chrominance circuit, text slicer, VBI-bypass, output formatting, power and test control. Philips Semiconductors Product specification 9-bit video input processor 8.4 Luminance processing SAA7113H The high frequency components of the luminance signal can be peaked (control for sharpness improvement via I2C-bus subaddress 09H, see Table 36) in two band-pass filters with selectable transfer characteristic. This signal is then added to the original (unpeaked) signal. For the resulting frequency characteristics see Figs 11 to 18. A switchable amplifier achieves common DC amplification, because the DC gains are different in both chrominance trap modes. The improved luminance signal is fed to the BCS control located in the chrominance processing block, see Fig.19. The 9-bit luminance signal, a digital CVBS format or a luminance format (S-VHS, HI8), is fed through a switchable prefilter. High frequency components are emphasized to compensate for loss. The following chrominance trap filter (f0 = 4.43 or 3.58 MHz centre frequency set according to the selected colour standard) eliminates most of the colour carrier signal. It should be bypassed via I2C-bit BYPS (subaddress 09H, bit 7) for S-video (S-VHS, HI8) signals. MGD139 handbook, full pagewidth 18 VY (dB) 6 (1) (2) (4) (3) -6 (1) (2) (4) (3) -18 -30 0 (2) 53H. 2 (3) 63H. 4 (4) 73H. 6 fY (MHz) 8 (1) 43H. Fig.11 Luminance control SA 09H, 4.43 MHz trap/CVBS mode, prefilter on, different aperture band-pass centre frequencies. 1999 Jul 01 16 Philips Semiconductors Product specification 9-bit video input processor SAA7113H MGD140 handbook, full pagewidth 18 VY (dB) 6 (1) (2) (3) (4) -6 (4) (3) (2) (1) -18 -30 0 2 4 6 fY (MHz) 8 (1) 40H. (2) 41H. (3) 42H. (4) 43H. Fig.12 Luminance control SA 09H, 4.43 MHz trap/CVBS mode, prefilter on, different aperture factors. MGD141 handbook, full pagewidth 18 VY (dB) 6 (1) (2) (4) (3) -6 (1) (2) (4) (3) -18 -30 0 (2) 13H. 2 (3) 23H. 4 (4) 33H. 6 fY (MHz) 8 (1) 03H. Fig.13 Luminance control SA 09H, 4.43 MHz trap/CVBS mode, prefilter off, different aperture band-pass centre frequencies. 1999 Jul 01 17 Philips Semiconductors Product specification 9-bit video input processor SAA7113H MGD142 handbook, full pagewidth 18 VY (dB) 6 (1) (2) (3) (4) -6 -18 -30 0 2 4 6 fY (MHz) 8 (1) C0H. (2) C1H. (3) C2H. (4) C3H. Fig.14 Luminance control SA 09H, Y/C mode, prefilter on, different aperture factors. MGD143 handbook, full pagewidth 18 VY (dB) 6 (1) (2) (3) (4) -6 -18 -30 0 2 4 6 fY (MHz) 8 (1) 80H. (2) 81H. (3) 82H. (4) 83H. Fig.15 Luminance control SA 09H, Y/C mode, prefilter off, different aperture factors. 1999 Jul 01 18 Philips Semiconductors Product specification 9-bit video input processor SAA7113H MGD144 handbook, full pagewidth 18 VY (dB) 6 (1) (2) (4) (3) (1) (2) (4) (3) -6 -18 -30 0 (2) 53H. 2 (3) 63H. 4 (4) 73H. 6 fY (MHz) 8 (1) 43H. Fig.16 Luminance control SA 09H, 3.58 MHz trap/CVBS mode, prefilter on, different aperture band-pass centre frequencies. MGD145 handbook, full pagewidth 18 VY (dB) 6 (1) (2) (3) (4) -6 (4) (3) (2) (1) -18 -30 0 2 4 6 fY (MHz) 8 (1) 40H. (2) 41H. (3) 42H. (4) 43H. Fig.17 Luminance control SA 09H, 3.58 MHz trap/CVBS mode, prefilter on, different aperture factors. 1999 Jul 01 19 Philips Semiconductors Product specification 9-bit video input processor SAA7113H MGD146 handbook, full pagewidth 18 VY (dB) 6 (1) (2) (4) (3) -6 (1) (2) (4) (3) -18 -30 0 2 4 6 fY (MHz) 8 (1) 03H. (2) 13H. (3) 23H. (4) 33H. Fig.18 Luminance control SA 09H, 3.58 MHz trap/CVBS mode, prefilter off, different aperture band-pass centre frequencies. 1999 Jul 01 20 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... dbook, full pagewidth 1999 Jul 01 LUM Philips Semiconductors 9-bit video input processor Y LUMINANCE CIRCUIT PREFILTER CHROMINANCE TRAP VARIABLE BAND-PASS FILTER WEIGHTING AND ADDING STAGE PREF BYPS VBLB BPSS0 BPSS1 PREF PREFILTER SYNC MACROVISION DETECTOR COPRO MATCHING AMPLIFIER APER0 APER1 VBLB CLOCK CIRCUIT CLOCKS VBLB PHASE DETECTOR FINE LINE-LOCKED CLOCK GENERATOR PHASE DETECTOR COARSE DAC6 AUFD HSB (7 : 0) HSS (7 : 0) FSEL HLCK 17 LLC SYNC SLICER 21 SYNCHRONIZATION CIRCUIT I2C-BUS CONTROL VNOI0 VNOI1 HTC (1 : 0) FIDT I2C-BUS INTERFACE VERTICAL PROCESSOR 24 23 26 RTS0 SCL SDA CLOCK GENERATION CIRCUIT 10 11 40 VDDA0 VSSA0 CE HPLL HTC (1 : 0) HTC (1 : 0) INCS DISCRETE TIME OSCILLATOR 2 CRYSTAL CLOCK GENERATOR 32 31 COUNTER LOOP FILTER 2 XTALI XTAL 27 MHB329 RTS1 Product specification SAA7113H Fig.19 Luminance and sync processing. Philips Semiconductors Product specification 9-bit video input processor 8.5 Synchronization 8.6 Clock generation circuit SAA7113H The prefiltered luminance signal is fed to the synchronization stage. Its bandwidth is further reduced to 1 MHz in a low-pass filter. The sync pulses are sliced and fed to the phase detectors where they are compared with the sub-divided clock frequency. The resulting output signal is applied to the loop filter to accumulate all phase deviations. Internal signals (e.g. HCL and HSY) are generated in accordance with analog front-end requirements. The loop filter signal drives an oscillator to generate the line frequency control signal LFCO, see Fig.19. The detection of `pseudo syncs' as part of the macrovision copy protection standard is also done within the synchronization circuit. The result is reported as flag COPRO within the decoder status byte at subaddress 1FH. The internal CGC generates all clock signals required for the video input processor. The internal signal LFCO is a digital-to-analog converted signal provided by the horizontal PLL. It is the multiple of the line frequency [6.75 MHz = 429 x fH (50 Hz) or 432 x fH (60 Hz)]. Internally the LFCO signal is multiplied by a factor of 2 and 4 in the PLL circuit (including phase detector, loop filtering, VCO and frequency divider) to obtain the output clock signals. The rectangular output clocks have a 50% duty factor. handbook, full pagewidth LFCO BAND PASS FC = LLC/4 ZERO CROSS DETECTION PHASE DETECTION LOOP FILTER OSCILLATOR LLC DIVIDER 1/2 DIVIDER 1/2 MHB330 LLC2 Fig.20 Block diagram of clock generation circuit. Table 1 Clock frequencies CLOCK XTAL LLC FREQUENCY (MHz) 24.576 27 13.5 6.75 3.375 8.7 Power-on reset and CE input A missing clock, insufficient digital or analog VDDA0 supply voltages (below 2.8 V) will initiate the reset sequence; all outputs are forced to 3-state (see Fig.21). It is possible to force a reset by pulling the Chip Enable (CE) to ground. After the rising edge of CE and sufficient power supply voltage, the outputs LLC and SDA return from 3-state to active, while RTS0, RTS1 and RTCO remain in 3-state and have to be activated via I2C-bus programming (see Table 2). LLC2 (internal) LLC4 (internal) LLC8 (virtual) 1999 Jul 01 22 Philips Semiconductors Product specification 9-bit video input processor SAA7113H handbook, full pagewidth POC V DDA ANALOG POC V DDD DIGITAL CLOCK PLL LLC CE POC LOGIC RESINT CLK0 POC DELAY RES CE XTAL LLCINT RESINT LLC RES (internal reset) some ms 20 to 200 s PLL-delay <1 ms 896 LCC digital delay 128 LCC MHB331 CE = chip enable input; XTAL = crystal oscillator output; LLCINT = internal system clock; RESINT = internal reset; LLC = line-locked clock output. Fig.21 Power-on control circuit. 1999 Jul 01 23 Philips Semiconductors Product specification 9-bit video input processor Table 2 Power-on control sequence PIN OUTPUT STATUS VPO7 to VPO0, RTCO, RTS0, RTS1, SDA and LLC are in high-impedance state LLC and SDA become active; VPO7 to VPO0, RTCO, RTS0 and RTS1 are held in high-impedance state VPO7 to VPO0, RTCO, RTS0 and RTS1 are held in high-impedance state SAA7113H INTERNAL POWER-ON CONTROL SEQUENCE Directly after power-on asynchronous reset Synchronous reset sequence Status after power-on control sequence 8.8 REMARKS direct switching to high-impedance for 20 to 200 ms internal reset sequence after power-on (reset sequence) a complete I2C-bus transmission is required Multi-standard VBI data slicer The multi-standard data slicer is a Vertical Blanking Interval (VBI) and Full Field (FF) video data acquisition block. In combination with software modules the slicer acquires most existing formats of broadcast VBI and FF data. The implementation and programming model of the multi-standard VBI data slicer is similar to the text slicer built in the "Multimedia Video Data Acquisition Circuit SAA5284". The circuitry recovers the actual clock phase during the clock-run-in-period, slices the data bits with the selected data rate, and groups them into bytes. The clock frequency, signals source, field frequency and accepted error count must be defined via the I2C-bus in subaddress 40H, AC1: bits D7 to D4. Table 3 Supported VBI standards STANDARD TYPE Teletext EuroWST, CCST European closed caption VPS Wide screen signalling bits US teletext (WST) US closed caption (line 21) Teletext VITC/EBU time codes (Europe) VITC/SMPTE time codes (USA) US NABTS MOJI (Japanese) Japanese format switch (L20/22) DATA RATE (Mbits/s) 6.9375 0.500 5 5 5.7272 0.503 6.9375 1.8125 1.7898 5.7272 5.7272 5 Several standards can be selected per VBI line. The supported VBI data standards are described in Table 3. The programming of the desired standards is done via I2C-bus subaddresses 41H to 57H (LCR2[7 : 0] to LCR24[7 : 0]); see detailed description in Chapter 8.10. To adjust the slicers processing to the signals source, there are offsets in horizontal and vertical direction available via the I2C-bus in subaddresses 5BH (bits 2 to 0), 59H (HOFF10 to HOFF0) and 5BH (bit 4), 5AH (VOFF8 to VOFF0). The formatting of the decoded VBI data is done within the output interface to the VPO-bus. For a detailed description of the sliced data format see Table 17. FRAMING CODE 27H 001 9951H 1E3C1FH 27H 001 programmable programmable programmable programmable programmable (A7H) programmable FC WINDOW WST625 CC625 VPS WSS WST525 CC525 general text VITC625 VITC625 NABTS Japtext HAM CHECK always always optional optional 1999 Jul 01 24 Philips Semiconductors Product specification 9-bit video input processor 8.9 VBI-raw data bypass SAA7113H For a 27 MHz VBI-raw data bypass the digitized CVBS signal is upsampled after AD-conversion. Suppressing of the back folded CVBS frequency components after upsampling is achieved by an interpolation filter; see Fig.22. V handbook, full pagewidth (dB) 0 -6 -12 -18 -24 -30 -36 -42 -48 -54 0 2 4 6 8 10 12 f (MHz) 14 6 MGG067 Fig.22 Interpolation filter for the upsampled CVBS signal. 1999 Jul 01 25 Philips Semiconductors Product specification 9-bit video input processor 8.10 Digital output port VPO7 to VPO0 SAA7113H The 8-bit VPO-bus can carry 16 data types in three different formats, selectable by the control registers LCR2 to LCR24 (see also Chapter 15, subaddresses 41H to 57H). Table 4 VPO-bus data formats and types DATA FORMAT sliced sliced sliced sliced sliced sliced raw sliced sliced sliced reserved sliced sliced sliced DATA TYPE teletext EuroWST, CCST European closed caption VPS Wide screen signalling bits US teletext (WST) US closed caption (line 21) oversampled CVBS data teletext VITC/EBU time codes (Europe) VITC/SMPTE time codes (USA) reserved US NABTS MOJI (Japanese) Japanese format switch (L20/22) NAME WST625 CC625 VPS WSS WST525 CC525 test line intercast general text VITC625 VITC625 - NABTS Japtext JFS NUMBER OF VALID BYTES SENT PER LINE 88 8 56 32 72 8 1440 programmable 88 26 26 - 72 74 56 1440 DATA TYPE NUMBER 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Note YUV 4 : 2 : 2 video component signal, VBI region YUV 4 : 2 : 2 video component signal, active video region active video 1. The number of valid bytes per line can be less for the sliced data format if standard not recognized (wrong standard or poor input signal). For each LCR value from 2 to 23 the data type can be programmed individually. LCR2 to LCR23 refer to line numbers. The selection in LCR24 values is valid for the rest of the corresponding field. The upper nibble contains the value for field 1 (odd), the lower nibble for field 2 (even). The relationship between LCR values and line numbers can be adjusted via VOFF8 to VOFF0 (located in subaddresses 5BH, bit 4 and 5AH, bits 7 to 0). The recommended values are 07H for 50 Hz sources and 0AH for 60 Hz sources, to accommodate line number conventions as used for PAL, SECAM and NTSC standards; see Tables 8 to 11. 1999 Jul 01 26 Philips Semiconductors Product specification 9-bit video input processor Some details about data types: * Active video (data type 15) component YUV 4 : 2 : 2 signal, 720 active pixels per line. Format and nominal levels are given in Fig.23 and Table 13. * Test line (data type 6), is similar to decoded YUV-data as in active video, with two exceptions: - vertical filter (chrominance comb filter for NTSC standards, PAL-phase-error correction) within the chrominance processing is disabled - peaking and chrominance trap are bypassed within the luminance processing, if I2C-bus bit VBLB is set. This data type is defined for future enhancements; it could be activated for lines containing standard test signals within the vertical blanking period; currently the most sources do not contain test lines. This data type is available only in lines with VREF = 0, see I2C-bus detail section, Table 45. Format and nominal levels are given in Fig.23 and Table 13. * Raw samples (data type 7) oversampled CVBS-signal for intercast applications; the data rate is 27 MHz. The horizontal range is programmable via HSB7 to HSB0, HSS7 to HSS0 and HDEL1 to HDEL0; Table 5 BIT 7 1 SAV/EAV format BIT 6 (F) field bit 1st field: F = 0; 2nd field: F = 1; for vertical timing see Tables 6 and 7 BIT 5 (V) vertical blanking bit VBI: V = 1; active video: V = 0; for vertical timing see Tables 6 and 7 BIT 4 (H) H = 0 in SAV; H = 1 in EAV SAA7113H see I2C-bus section subaddresses 06H, 07H and 10H and Tables 33, 34 and 46. Format and nominal levels are given in Fig.24 and Table 15. * Sliced data (various standards, data types 0 to 5 and 8 to 14). The format is given in Table 17. The data type selections by LCR are overruled by setting VIPB (subaddress 11H bit 1) to logic 1. This setting is mainly intended for device production tests. The VPO-bus carries the upper or lower 8 bits of the two ADCs depending on the ADLSB (subaddress 13H bit 7) setting. The output configuration is done via MODE3 to MODE0 settings (subaddress 02H bits 3 to 0, see Table 27). If the YC-mode is selected, the VPO-bus carries the multiplexed output signals of both ADCs, in CVBS-mode the output of only one ADC. No timing reference codes are generated in this mode. Note: The LSBs (bit 0) of the ADCs are available on pins RTS0 or RTS1. See Chapter 15, subaddress 12H for details. The SAV/EAV timing reference codes define start and end of valid data regions. BIT 3 BIT 2 BIT 1 BIT 0 (P3) (P2) (P1) (P0) reserved; evaluation not recommended (protection bits according to ITU 656) The generation of the H-bit and consequently the timing of SAV/EAV corresponds to the selected data format. H = 0 during active data region. For all data formats excluding data type 7 (raw data), the length of the active data region is 1440 LLC. For the YUV 4 : 2 : 2 formats (data types 15 and 6) every clock cycle within this range contains valid data, see Table 13. The sliced data stream (various standards, data types 0 to 5 and 8 to 14; see Table 17) contains also invalid cycles marked as 00H. The length of the raw data region (data type 7) is programmable via HSB7 to HSB0 and HSS7 to HSS0 (subaddresses 06H and 07H; see Fig.24). During horizontal blanking period between EAV and SAV the ITU-blanking code sequence `-80-10-80-10-...' is transmitted. The position of the F-bit is constant according to ITU 656 (see Tables 6 and 7). The V-bit can be generated in four different ways (see Tables 6 and 7) controlled via OFTS1 and OFTS0 (subaddress 10H, bits 7 and 6), VRLN (subaddress 10H, bit 3) and LCR2 to LCR24 (subaddresses 41H to 57H). F and V bits change synchronously with the EAV code. 1999 Jul 01 27 Philips Semiconductors Product specification 9-bit video input processor Table 6 525 lines/60 Hz vertical timing V LINE NUMBER F (ITU 656) OFTS1 = 0; OFTS0 = 0 (ITU 656) 1 1 0 0 0 0 0 1 1 0 0 0 0 OFTS1 = 0; OFTS0 = 1 VRLN = 0 VRLN = 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 0 0 0 1 1 1 1 0 0 0 SAA7113H OFTS1 = 1; OFTS0 = 0 according to selected data type via LCR2 to LCR24 (subaddresses 41H to 57H): data types 0 to 14: V = 1; data type 15: V = 0 1 to 3 4 to 19 20 21 22 to 261 262 263 264 and 265 266 to 282 283 284 285 to 524 525 Table 7 1 0 0 0 0 0 0 0 1 1 1 1 1 625 lines/50 Hz vertical timing V LINE NUMBER F (ITU 656) OFTS1 = 0; OFTS0 = 0 (ITU 656) 1 0 0 0 1 1 0 0 0 1 OFTS1 = 0; OFTS0 = 1 VRLN = 0 VRLN = 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 0 1 OFTS1 = 1; OFTS0 = 0 according to selected data type via LCR2 to LCR24 (subaddresses 41H to 57H): data types 0 to 14: V = 1; data type 15: V = 0 1 to 22 23 24 to 309 310 311 and 312 313 to 335 336 337 to 622 623 624 and 625 0 0 0 0 0 1 1 1 1 1 1999 Jul 01 28 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1999 Jul 01 29 LCR (VOFF = 00AH; HOFF = 354H; FOFF = 1; FISET = 1) Line number (1st field) Line number (2nd field) LCR (VOFF = 007H; HOFF = 354H; FOFF = 1; FISET = 0) Philips Semiconductors Table 8 Relationship of LCR to line numbers in 525 lines/60 Hz systems (part 1) 9-bit video input processor VERTICAL LINE OFFSET VOFF8 TO VOFF0 = 00AH; HORIZONTAL PIXEL OFFSET HOFF10 TO HOFF0 = 354H, FOFF = 1, FISET = 1 Line number (1st field) Line number (2nd field) 519 257 520 258 521 259 522 260 523 261 524 262 525 263 1 264 2 265 2 3 266 3 4 267 4 5 268 5 6 269 6 7 270 7 8 271 8 9 272 9 active video active video equalization pulses equalization pulses serration pulses serration pulses equalization pulses equalization pulses LCR 24 (VOFF = 00AH; HOFF = 354H; FOFF = 1; FISET = 1) Table 9 Relationship of LCR to line numbers in 525 lines/60 Hz systems (part 2) VERTICAL LINE OFFSET VOFF8 TO VOFF0 = 00AH; HORIZONTAL PIXEL OFFSET HOFF10 TO HOFF0 = 354H, FOFF = 1, FISET = 1 Line number (1st field) Line number (2nd field) 10 273 10 11 274 11 12 275 12 13 276 13 14 277 14 15 278 15 16 279 16 17 280 17 18 281 18 19 282 19 20 283 20 21 284 21 22 285 22 23 286 23 nominal VBI-lines F1 nominal VBI-lines F2 active video active video Table 10 Relationship of LCR to line numbers in 625 lines/50 Hz systems (part 1) VERTICAL LINE OFFSET VOFF8 TO VOFF0 = 007H; HORIZONTAL PIXEL OFFSET HOFF10 TO HOFF0 = 354H, FOFF = 1, FISET = 0 621 309 24 622 310 623 311 624 312 625 313 1 314 2 315 2 3 316 3 4 317 4 5 318 5 active video active video equalization pulses serration pulses equalization pulses serration pulses equalization pulses equalization pulses Product specification SAA7113H This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1999 Jul 01 30 Philips Semiconductors Table 11 Relationship of LCR to line numbers in 625 lines/50 Hz systems (part 2) 9-bit video input processor VERTICAL LINE OFFSET VOFF8 TO VOFF0 = 007H; HORIZONTAL PIXEL OFFSET HOFF10 TO HOFF0 = 354H, FOFF = 1, FISET = 0 Line number (1st field) Line number (2nd field) 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 active video 323 10 324 11 325 12 326 13 327 14 328 15 329 16 330 17 331 18 332 19 333 20 334 21 335 22 336 23 337 24 338 active video 25 nominal VBI-lines F1 319 320 321 7 8 322 9 nominal VBI-lines F2 LCR 6 (VOFF = 007H; HOFF = 354H; FOFF = 1; FISET = 0) Table 12 Location of related programming registers NAME VOFF8 to VOFF0 HOFF10 to HOFF0 FOFF FISET 5B, D4 and 5A, D7 to D0 5B, D2 to D0 and 59, D7 to D0 5B, D7 40, D7 SUBADDRESS, BITS Product specification SAA7113H Philips Semiconductors Product specification 9-bit video input processor SAA7113H handbook, full pagewidth +255 +235 white +255 +240 +212 blue 100% blue 75% +255 +240 +212 red 100% red 75% +128 LUMINANCE 100% +128 U-COMPONENT colourless +128 V-COMPONENT colourless +44 +16 0 black +16 0 yellow 75% yellow 100% +44 +16 0 cyan 75% cyan 100% MGC634 a. Y output range. b. U output range (CB). c. V output range (CR). Equations for modification to the YUV levels via BCS control I2C-bus bytes BRIG, CONT and SATN. Luminance: CONT Y OUT = Int ----------------- x ( Y - 128 ) + BRIG 71 Chrominance: SATN UV OUT = Int ---------------- x ( C R, C B - 128 ) + 128 64 It should be noted that the resulting levels are limited to 1 to 254 in accordance with ITU-601/656 standard. Fig.23 YUV 4 : 2 : 2 levels on the 8-bit VPO-bus (data types 6 and 15). Table 13 YUV data format on the 8-bit VPO-bus (data types 6 and 15) BLANKING PERIOD ... 80 10 TIMING REFERENCE CODE 720 PIXELS YUV 4 : 2 : 2 DATA TIMING REFERENCE CODE BLANKING PERIOD 10 ... FF 00 00 SAV CB0 Y0 CR0 Y1 CB2 Y2 ... CR718 Y719 FF 00 00 EAV 80 Table 14 Explanation to Table 13 NAME SAV CBn Yn CRn EAV EXPLANATION start of active video range; see Tables 5 to 7 U (B - Y) colour difference component, pixel number n = 0, 2, 4 to 718 Y (luminance) component, pixel number n = 0, 1, 2, 3 to 719 V (R - Y) colour difference component, pixel number n = 0, 2, 4 to 718 end of active video range; see Tables 5 to 7 1999 Jul 01 31 Philips Semiconductors Product specification 9-bit video input processor SAA7113H handbook, full pagewidth +255 +209 white +255 +199 white LUMINANCE LUMINANCE +71 +60 SYNC 1 black black shoulder +60 SYNC black shoulder = black sync bottom 1 sync bottom MGD700 a. For sources containing 7.5 IRE black level offset (e.g. NTSC - M). b. For sources not containing black level offset. VBI data levels are not dependent on BCS settings. Fig.24 Raw data levels on the 8-bit VPO-bus (data type 8). Table 15 Raw data format on the 8-bit VPO-bus (data type 8) BLANKING PERIOD ... 80 10 TIMING REFERENCE CODE OVERSAMPLED CVBS SAMPLES Yn TIMING REFERENCE CODE BLANKING PERIOD 10 ... FF 00 00 SAV Y0 Y1 Y2 Y3 Y4 Y5 ... Yn - 1 FF 00 00 EAV 80 Table 16 Explanation to Table 15 NAME SAV Yi EAV EXPLANATION start of raw sample range; see Tables 5 to 7 oversampled raw sample stream (CVBS signal), n = 0, 1, 2, 3 to n; n is programmable via HSB and HSS; see Sections 15.2.7 and 15.2.8 end of raw sample range; see Tables 5 to 7 1999 Jul 01 32 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1999 Jul 01 33 IDI1 IDI2 DLNn DLHn EAV Notes 1. Inverted EP (bit 7); for EP see note 2. 2. Even parity (bit 6) of bits 5 to 0. 3. Odd parity (bit 7) of bits 6 to 0. Product specification Philips Semiconductors Table 17 Sliced data format on the 8-bit VPO-bus (data types 0 to 5 and 8 to 14) 9-bit video input processor BLANKING PERIOD ... 80 10 TIMING REFERENCE CODE FF 00 00 SAV INTERNAL HEADER SDID DC IDI1 IDI2 DLN1 SLICED DATA DHN1 ... DLNn DHNn TIMING REFERENCE CODE FF 00 00 EAV BLANKING PERIOD 80 10 ... Table 18 Explanation to Table 17 NAME SAV SDID DC start of active data; see Tables 5 to 7 sliced data identification: NEP(1), EP(2), SDID5 to SDID0, freely programmable via I2C-bus subaddress 5EH, D5 to D0, e. g. to be used as source identifier Dword count: NEP(1), EP(2), DC5 to DC0; DC is inserted for software compatibility reasons to SAA7112, but does not represent any relevant information for SAA7113H applications. DC describes the number of succeeding 32-bit words: DC = 14(C + n), where C = 2 (the two data identification bytes IDI1 and IDI2) and n = number of decoded bytes according to the chosen text standard. As the sliced data are transmitted nibble wise, the maximum number of bytes transmitted (NBT) starting at IDI1 results to: NBS = (DC x 8) - 2 DC can vary between 1 and 11, depending on the selected data type. Note that the number of bytes actually transmitted can be less than NBT for two reasons: 1. result of DC would result to a non-integer value (DC is always rounded up) 2. standard not recognized (wrong standard or poor input signal) internal data identification 1: OP(3), FID (field 1 = 0, field 2 = 1), LineNumber8 to LineNumber3 internal data identification 2: OP(3), LineNumber2 to LineNumber0, DataType3 to DataType0; see Table 4 sliced data LOW nibble, format: NEP(1), EP(2), D3 to D0, 1, 1 sliced data HIGH nibble, format: NEP(1), EP(2), D7 to D4, 1, 1 end of active data; see Tables 5 to 7 EXPLANATION SAA7113H Philips Semiconductors Product specification 9-bit video input processor 8.11 RTCO output SAA7113H Table 19 Digital output control via RTS1 (enabled by bits RTSE13 to RTSE10 = 0) OEYC 0 1 0 1 9 DOT (RTS1) 0 0 1 1 VPO7 TO VPO0 Z active Z Z The real-time control and status output signal contains serial information about the actual system clock (increment of the HPLL), subcarrier frequency, increment and phase (via reset) of the FSC-PLL and PAL sequence bit. The signal can be used for various applications in external circuits, e.g. in a digital encoder to achieve clean encoding. The SAA7113H supports RTC level 3.1 (see external document "RTC Functional Description", available on request). 8.12 RTS0, RTS1 terminals BOUNDARY SCAN TEST These two pins are multi functional inputs/output controlled by I2C-bus bits RTSE03 to RTSE00 and RTSE13 to RTSE10, located in subaddress 12H; see Tables 49 and 50. The RTS0 terminal can be strapped to ground via a 3.3 k resistor to change the I2C-bus slave address from default 4AH/4BH to 48H/49H (the strapping information is read only during the reset sequence). The RTS1 terminal can be configured as Data Output to 3-state (DOT) input by RTSE13 to RTSE10 = 0000 to control the VPO port (bits 7 to 0) via hardware according to Table 19. The SAA7113H has built in logic and 5 dedicated pins to support boundary scan testing which allows board testing without special hardware (nails). The SAA7113H follows the "IEEE Std. 1149.1 - Standard Test Access Port and Boundary-Scan Architecture" set by the Joint Test Action Group (JTAG) chaired by Philips. The 5 special pins are Test Mode Select (TMS), Test Clock (TCK), Test Reset (TRST), Test Data Input (TDI) and Test Data Output (TDO). The BST functions BYPASS, EXTEST, INTEST, SAMPLE, CLAMP and IDCODE are all supported (see Table 20). Details about the JTAG BST-TEST can be found in the specification "IEEE Std. 1149.1". A file containing the detailed Boundary Scan Description Language (BSDL) description of the SAA7113H is available on request. Table 20 BST instructions supported by the SAA7113H INSTRUCTION BYPASS EXTEST SAMPLE DESCRIPTION This mandatory instruction provides a minimum length serial path (1 bit) between TDI and TDO when no test operation of the component is required. This mandatory instruction allows testing of off-chip circuitry and board level interconnections. This mandatory instruction can be used to take a sample of the inputs during normal operation of the component. It can also be used to preload data values into the latched outputs of the boundary scan register. This optional instruction is useful for testing when not all ICs have BST. This instruction addresses the bypass register while the boundary scan register is in external test mode. This optional instruction will provide information on the components manufacturer, part number and version number. This optional instruction allows testing of the internal logic (no support for customers available). This private instruction allows testing by the manufacturer (no support for customers available). CLAMP IDCODE INTEST USER1 1999 Jul 01 34 Philips Semiconductors Product specification 9-bit video input processor 9.1 Initialization of boundary scan circuit SAA7113H When the IDCODE instruction is loaded into the BST instruction register, the identification register will be connected between TDI and TDO of the IC. The identification register will load a component specific code during the CAPTURE_DATA_REGISTER state of the TAP controller and this code can subsequently be shifted out. At board level this code can be used to verify component manufacturer, type and version number. The device identification register contains 32 bits, numbered 31 to 0, where bit 31 is the most significant bit (nearest to TDI) and bit 0 is the least significant bit (nearest to TDO); see Fig.25. The TAP (Test Access Port) controller of an IC should be in the reset state (TEST_LOGIC_RESET) when the IC is in functional mode. This reset state also forces the instruction register into a functional instruction such as IDCODE or BYPASS. To solve the power-up reset, the standard specifies that the TAP controller will be forced asynchronously to the TEST_LOGIC_RESET state by setting the TRST pin LOW. 9.2 Device identification codes A device identification register is specified in "IEEE Std. 1149.1b-1994". It is a 32-bit register which contains fields for the specification of the IC manufacturer, the IC part number and the IC version number. Its biggest advantage is the possibility to check for the correct ICs mounted after production and determination of the version number of ICs during field service. handbook, full pagewidth MSB 31 TDI 28 27 0111000100010011 12 11 00000010101 1 LSB 0 1 TDO nnnn 4-bit version code 16-bit part number 11-bit manufacturer identification MHB332 Fig.25 32 bits of identification code. 1999 Jul 01 35 Philips Semiconductors Product specification 9-bit video input processor SAA7113H 10 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); all ground pins connected together and all supply pins connected together. SYMBOL VDDD VDDA ViA VoA ViD VoD VSS Tstg Tamb Tamb(bias) Vesd Note 1. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k resistor. 11 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 64 UNIT K/W PARAMETER digital supply voltage analog supply voltage input voltage at analog inputs output voltage at analog output input voltage at digital inputs and outputs output voltage at digital outputs voltage difference between VSSA(all) and VSS(all) storage temperature operating ambient temperature operating ambient temperature under bias electrostatic discharge all pins note 1 outputs in 3-state outputs active CONDITIONS MIN. -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 - -65 0 -10 -2000 MAX. +4.6 +4.6 VDDA + 0.5 (4.6 max) VDDA + 0.5 +5.5 VDDD + 0.5 100 +150 70 +80 +2000 V V V V V V mV C C C V UNIT 1999 Jul 01 36 Philips Semiconductors Product specification 9-bit video input processor 12 CHARACTERISTICS VDDD = 3.0 to 3.6 V; VDDA = 3.1 to 3.5 V; Tamb = 25 C; unless otherwise specified. SYMBOL Supplies VDDD IDDD PD VDDA IDDA PA PA+D PA+D(pd) Analog part Iclamp Vi(p-p) clamping current input voltage (peak-to-peak value) VI = 0.9 V DC for normal video levels 1 V (p-p), termination 18/56 and AC coupling required; coupling capacitor = 47 nF clamping current off fi = 5 MHz at -3 dB - 0.5 8 0.7 - digital supply voltage digital supply current digital power analog supply voltage analog supply current analog power analog and digital power analog and digital power in CE connected to ground power-down mode VDDA VDDD + 200 mV AOSL1 to AOSL0 = 0 3.0 - - 3.1 - - - - 3.3 32 0.10 3.3 90 0.30 0.40 0.07 PARAMETER CONDITIONS MIN. TYP. SAA7113H MAX. UNIT 3.6 35 - 3.5 - - - - V mA W V mA W W W A V 1.4 Zi Ci cs B diff input impedance input capacitance channel crosstalk 200 - - - - - - - - 10 -50 - - k pF dB 9-bit analog-to-digital converters bandwidth differential phase (amplifier plus anti-alias filter bypassed) differential gain (amplifier plus anti-alias filter bypassed) ADC clock frequency DC differential linearity error DC integral linearity error 7 2 MHz deg Gdiff - 2 - % fclk(ADC) DLE ILE 12.8 - - - 0.7 1 14.3 - - MHz LSB LSB 1999 Jul 01 37 Philips Semiconductors Product specification 9-bit video input processor SAA7113H SYMBOL Digital inputs VIL(SCL,SDA) VIH(SCL,SDA) VIL(xtal) VIH(xtal) VIL(n) VIH(n) ILI Ci Ci(n) PARAMETER CONDITIONS MIN. -0.5 0.7VDDD -0.3 2.0 -0.3 2.0 - - - - - - - - - - TYP. MAX. UNIT LOW-level input voltage pins SDA and SCL HIGH-level input voltage pins SDA and SCL LOW-level CMOS input voltage pin XTALI HIGH-level CMOS input voltage pin XTALI LOW-level input voltage all other inputs HIGH-level input voltage all other inputs input leakage current input capacitance input capacitance all other inputs outputs at 3-state +0.3VDDD VDDD + 0.5 +0.8 VDDD + 0.3 +0.8 5.5 10 8 5 V V V V V V A pF pF - - Digital outputs VOL(SCL,SDA) VOL VOH VOL(clk) VOH(clk) LOW-level output voltage pins SDA and SCL LOW-level output voltage HIGH-level output voltage LOW-level output voltage for LLC clock HIGH-level output voltage for LLC clock SDA/SCL at 3 mA (6 mA) sink current VDDD = max; IOL = 2 mA VDDD = min; IOH = -2 mA - 0 2.4 -0.5 2.4 - - - - - 0.4 (0.6) 0.4 VDDD + 0.5 +0.6 VDDD + 0.5 V V V V V RTS1 (DOT) input timing tSU;DAT tHD;DAT CL tOHD;DAT tPD tPDZ input data set-up time input data hold time 13 3 - - - - - - - - ns ns Data and control output timing; note 1 output load capacitance output hold time propagation delay propagation delay to 3-state CL = 15 pF CL = 25 pF 15 4 - - 40 - 22 22 pF ns ns ns 1999 Jul 01 38 Philips Semiconductors Product specification 9-bit video input processor SAA7113H SYMBOL PARAMETER CONDITIONS MIN. - - - - - - TYP. MAX. UNIT Clock output timing (LLC); note 2 CL(LLC) Tcy LLC tr tf XTALI fHn fH/fHn fSCn output load capacitance cycle time duty factors for tLLCH/tLLC rise time LLC fall time LLC LLC CL = 25 pF 15 35 40 - - 40 39 60 5 5 pF ns % ns ns Clock input timing (XTALI) duty factor for tXTALIH/tXTALI nominal frequency nominal line frequency permissible static deviation 50 Hz field 60 Hz field Subcarrier PLL nominal subcarrier frequency PAL BGHIN NTSC M; NTSC-Japan PAL M combination-PAL N fSC fn f/fn Tf/fn(T) lock-in range Crystal oscillator nominal frequency permissible nominal frequency deviation permissible nominal frequency deviation with temperature 3rd harmonic; note 3 - - - 24.576 - - - 50 20 MHz 10-6 10-6 - - - - 400 4433619 3579545 3575612 3582056 - - - - - - Hz Hz Hz Hz Hz 40 - - - 60 - - 5.7 % Horizontal PLL 15625 15734 - Hz Hz % CRYSTAL SPECIFICATION (X1) Tamb(X1) CL Rs C1 C0 Notes 1. The levels must be measured with load circuits; 1.2 k at 3 V (TTL load); CL = 50 pF. 2. The effects of rise and fall times are included in the calculation of tOHD;DAT, tPD and tPDZ. Timings and levels refer to drawings and conditions illustrated in Fig.26. 3. Order number: Philips 4322 143 05291. operating ambient temperature load capacitance series resonance resistor motional capacitance parallel capacitance 0 8 - - - - - 40 1.5 20% 3.5 20% 70 - 80 - - C pF fF pF 1999 Jul 01 39 Philips Semiconductors Product specification 9-bit video input processor Table 21 Processing delay FUNCTION Without amplifier or anti-alias filter With amplifier, without anti-alias filter With amplifier and anti-alias filter TYPICAL ANALOG DELAY AI22 -> ADCIN (AOUT) (ns) 15 25 75 SAA7113H DIGITAL DELAY ADCIN -> VPO (LLC CLOCKS); YDEL2 TO YDEL0 = 0 157 1999 Jul 01 40 Philips Semiconductors Product specification 9-bit video input processor 13 TIMING DIAGRAMS SAA7113H handbook, full pagewidth t LLC t LLCL 2.6 V 1.5 V 0.6 V tr CLOCK OUTPUT LLC tf t LLCH t PD t OHD;DAT OUTPUTS VPO, RTCO, RTS0, RTS1 2.4 V 0.6 V MHB333 Fig.26 Clock/data output timing. handbook, full pagewidth LLC tSU tHD RTS1 (DOT) tOHD VPO MHB334 tPDZ tPD Fig.27 RTS1 input (DOT) timing. 1999 Jul 01 41 Philips Semiconductors Product specification 9-bit video input processor SAA7113H handbook, full pagewidth CVBS input 28 x 1/LLC RAW DATA on VPO-bus 157 x 1/LLC burst burst processing delay CVBS->VPO(2) Y-DATA on VPO-bus RTS0/1 HREF (50 Hz) 720 x 2/LLC 15 x 2/LLC RTS0/1 (PLIN)(1) 0 sync clipped 12 x 2/LLC 144 x 2/LLC 55 x 2/LLC 4/LLC RTS0/1 HS RTS0/1 HS (50 Hz) 108 programming range (step size: 8/LLC) RTS0/1 HREF (60 Hz) 11 x 2/LLC 16 x 2/LLC 720 x 2/LLC RTS0/1 HS (60 Hz) RTS0/1 HS (60 Hz) programming range (step size: 8/LLC) -106 MHB335 0 -107 138 x 2/LLC 107 0 (1) PLIN is switched to outputs RTS0 and/or RTS1 via I2C-bus bits RTSE13 to RTSE10 and/or RTSE03 to RTSE00. (2) See Table 21. Fig.28 Horizontal timing diagram. 1999 Jul 01 42 Philips Semiconductors Product specification 9-bit video input processor SAA7113H handbook, full pagewidth 622 623 624 625 1 2 3 4 5 6 7 8 22 23 input CVBS RTS0/1 HREF RTS0/1 VREF VRLN = 1(1) RTS0/1 VREF VRLN = 0(1) RTS0/1 VS RTS0/1 ODD RTS0/1 V123(3) RTS0/1 FID(2) 499 x 2/LLC (a) 1st field 310 input CVBS 311 312 313 314 315 316 317 318 319 320 335 336 337 RTS0/1 HREF RTS0/1 VREF VRLN = 1(1) RTS0/1 VREF VRLN = 0(1) 67 x 2/LLC RTS0/1 VS RTS0/1 ODD RTS0/1 V123(3) RTS0/1 FID(2) MHB336 (b) 2nd field HREF: selectable on RTS0 and/or RTS1 via I2C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = 7H. ODD: selectable on RTS0 and/or RTS1 via I2C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = AH. VS: selectable on RTS0 and/or RTS1 via I2C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = BH. V123: selectable on RTS0 and/or RTS1 via I2C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = CH. VREF: selectable on RTS0 and/or RTS1 via I2C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = EH. FID: selectable on RTS0 and/or RTS1 via I2C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = FH. (1) VREF range short or long can be programmed via I2C-bus bit VRLN. The luminance peaking and the chrominance trap are bypassed during VREF = 0 if I2C-bus bit VBLB is set to logic 1. The chrominance delay line (chrominance-comb filter for NTSC, phase error correcting for PAL) is disabled during VREF = 0. (2) FID changing line number and polarity programmable via VSTA8 to VSTA0 and FIDP, see Table 52. (3) The inactive going edge of the V123-signal indicates whether the field is odd or even. If HREF is active during the falling edge of V123, the field is odd. If HREF is inactive during the falling edge of V123, the field is even. The specific position of the slope is dependent on the internal processing delay and may change a few clock cycles from version to version. Fig.29 Vertical timing diagram for 50 Hz [nominal input signal, VNL in normal mode (VNOI = 00), HPLL in VCR or fast mode (HTC = 01 or 11)]. 1999 Jul 01 43 Philips Semiconductors Product specification 9-bit video input processor SAA7113H handbook, full pagewidth 522 (525) 523 (1) 524 (2) 525 (3) 1 (4) 2 (5) 3 (6) 4 (7) 5 (8) 6 (9) 7 (10) 8 (11) 17 (20) 18 (21) 19 (22)(1) input CVBS RST0/1 HREF VRLN = 1(2) RTS0/1 VREF VRLN = 0(2) RTS0/1 VREF 520 x 2/LLC RTS0/1 VS RTS0/1 ODD RTS0/1 V123(4) RTS0/1 FID(3) (a) 1st field 259 (262) input CVBS RTS0/1 HREF VRLN = 1(3) (2) RTS0/1 VREF VRLN = 0(3) (2) RTS0/1 VREF 81 x 2/LLC RTS0/1 VS RTS0/1 ODD RTS0/1 V123(4) RTS0/1 FID(3) 260 (263) 261 (264) 262 (265) 263 (266) 264 (267) 265 (268) 266 (269) 267 (270) 268 (271) 269 (272) 270 (273) 271 (274) 280 (283) 281 (284) 282 (285)(1) (b) 2nd field HREF: selectable on RTS0 and/or RTS1 via bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = 7H. ODD: selectable on RTS0 and/or RTS1 via I2C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = AH. VS: selectable on RTS0 and/or RTS1 via I2C-bus bits RTSE03 to 00 and/or RTSE13 to RTSE10 = BH. V123: selectable on RTS0 and/or RTS1 via I2C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = CH. VREF: selectable on RTS0 and/or RTS1 via I2C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = EH. FID: selectable on RTS0 and/or RTS1 via I2C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = FH. (1) Line numbers in parenthesis refer to ITU line counting. (2) VREF range short or long can be programmed via I2C-bus bit VRLN. The luminance peaking and the chrominance trap are bypassed during VREF = 0 if I2C-bus bit VBLB is set to logic 1. The chrominance delay line (chrominance-comb filter for NTSC, phase error correcting for PAL) is disabled during VREF = 0. I2C-bus MHB337 (3) FID changing line number and polarity programmable via VSTA8 to VSTA0 and FIDP, see Table 52. (4) The inactive going edge of the V123-signal indicates whether the field is odd or even. If HREF is active during the falling edge of V123, the field is odd. If HREF is inactive during the falling edge of V123, the field is even. The specific position of the slope is dependent on the internal processing delay and may change a few clock cycles from version to version. Fig.30 Vertical timing diagram for 60 Hz [nominal input signal, VNL in normal mode (VNOI = 00), HPLL in VCR or fast mode (HTC = 01 or 11)]. 1999 Jul 01 44 Philips Semiconductors Product specification 9-bit video input processor 14 APPLICATION INFORMATION SAA7113H handbook, full pagewidth VDDD VDDA C8 C9 100 nF BST VDDA0 VDDA1 VDDA2 n.c. n.c. n.c. TMS TDO TCK TDI VSSD VDDDE1 VDDDE2 VDDDA VDDDI TRST C15 100 nF C14 C13 100 nF 100 nF C12 100 nF VSSD 100 nF C7 100 nF VSSA 10 R10 18 R4 VSSA 56 R9 18 R3 VSSA 56 R8 18 R2 VSSA 56 R7 18 R1 VSSA 56 VDDD R5 1 k CE SCL SDA C19 47 nF VSSA C20 47 nF XTAL Q1 (24.576 MHz) 10 H C16 1 nF C17 C18 XTALI AI2D 44 AI1D 40 24 23 C1 47 nF AI11 4 C2 47 nF AI12 7 C3 47 nF AI21 43 C4 47 nF AI22 1 3 42 39 38 36 37 8 18 34 29 33 12 13 14 15 19 20 21 22 VPO7 VPO6 VPO5 VPO4 VPO3 VPO2 VPO1 VPO0 SAA7113H 25 27 26 RTCO RTS1 RTS0 AOUT LLC 9 5 17 31 32 11 VSSA0 2 VSSA1 41 VSSA2 6 AGND 16 28 VSSDE1 VSSDI 30 35 VSSDA VSSDE2 MHB349 L1 10 pF 10 pF VSSD VSSA VSSD Fig.31 Application diagram. 1999 Jul 01 45 Philips Semiconductors Product specification 9-bit video input processor SAA7113H handbook, full pagewidth quartz (3rd harmonic) 24.576 MHz XTAL C= 10 pF XTALI 31 XTAL 31 SAA7113H 32 XTALI 32 SAA7113H L = 10 H 20% C= 10 pF C= 1 nF MHB338 a. With quartz crystal. b. With external clock. Order number: Philips 4322 143 05291. Fig.32 Oscillator application. 15 I2C-BUS DESCRIPTION 15.1 I2C-bus format handbook, full pagewidth S SLAVE ADDRESS W ACK-s SUBADDRESS ACK-s DATA data transferred (n bytes + acknowledge) ACK-s P MHB339 Fig.33 Write procedure. 1999 Jul 01 46 Philips Semiconductors Product specification 9-bit video input processor SAA7113H handbook, full pagewidth S Sr SLAVE ADDRESS W SLAVE ADDRESS R ACK-s ACK-s SUBADDRESS DATA ACK-s ACK-m P data transferred (n bytes + acknowledge) MHB340 Fig.34 Read procedure (combined format). Table 22 Description of I2C-bus format; note 1 CODE S Sr Slave address W Slave address R ACK-s ACK-m Subaddress Data P X = LSB slave address Subaddresses START condition repeated START condition 0100 1010 (= 4AH, default) or 0100 1000 (= 48H, if pin RTS0 strapped to ground via a 3.3 k resistor) 0100 1011 (= 4BH, default) or 0100 1001 (= 49H, if pin RTS0 strapped to ground via a 3.3 k resistor) acknowledge generated by the slave acknowledge generated by the master subaddress byte; see Table 24 data byte; see Table 24; note 2 STOP condition read/write control bit; X = 0, order to write (the circuit is slave receiver); X = 1, order to read (the circuit is slave transmitter) 00H chip version 01H to 05H front-end part 06H to 13H decoder part 14H reserved 15H to 17H decoder part 18H to 1EH reserved 1FH video decoder status byte 20H to 3FH reserved 40H to 60H general purpose data slicer 63H to FFH reserved Notes 1. The SAA7113H supports the `fast mode' I2C-bus specification extension (data rate up to 400 kbits/s). 2. If more than one byte DATA is transmitted the subaddress pointer is automatically incremented. read only read and write read and write - read and write - read only - read and write - DESCRIPTION 60H to 62H general purpose data slicer status read only 1999 Jul 01 47 Philips Semiconductors Product specification 9-bit video input processor Table 23 Slave address READ 4BH 49H 4AH 48H WRITE default RTS0 strapped to ground DESCRIPTION SAA7113H 1999 Jul 01 48 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1999 Jul 01 49 Philips Semiconductors Table 24 I2C-bus receiver/transmitter overview 9-bit video input processor REGISTER FUNCTION Chip version (read only) Increment delay Analog input control 1 Analog input control 2 Analog input control 3 Analog input control 4 Horizontal sync start Horizontal sync stop Sync control Luminance control Luminance brightness Luminance contrast Chroma saturation Chroma hue control Chroma control Chroma gain control Format/delay control Output control 1 Output control 2 Output control 3 Reserved V_GATE1_START V_GATE1_STOP V_GATE1_MSB Reserved Status byte (read only, OLDSB = 0) Status byte (read only, OLDSB = 1) Reserved SUBADDR. (HEX) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 to 1E 1F 1F 20 to 3F D7 ID07 (1) D6 ID06 (1) D5 ID05 (1) D4 ID04 (1) D3 - IDEL3 MODE3 HOLDG GAI13 GAI23 HSB3 HSS3 HTC0 VBLB BRIG3 CONT3 SATN3 HUEC3 DCCF CGAIN3 VRLN OEYC RTSE03 FIDP (1) D2 - IDEL2 MODE2 GAFIX GAI12 GAI22 HSB2 HSS2 HPLL UPTCV BRIG2 CONT2 SATN2 HUEC2 FCTC CGAIN2 YDEL2 OERT RTSE02 (1) (1) D1 - IDEL1 MODE1 GAI28 GAI11 GAI21 HSB1 HSS1 VNOI1 APER1 BRIG1 CONT1 SATN1 HUEC1 CHBW1 CGAIN1 YDEL1 VIPB RTSE01 AOSL1 (1) D0 - IDEL0 MODE0 GAI18 GAI10 GAI20 HSB0 HSS0 VNOI0 APER0 BRIG0 CONT0 SATN0 HUEC0 CHBW0 CGAIN0 YDEL0 COLO RTSE00 AOSL0 (1) FUSE1 (1) FUSE0 HLNRS GAI16 GAI26 HSB6 HSS6 FSEL PREF BRIG6 CONT6 SATN6 HUEC6 CSTD2 CGAIN6 OFTS0 CM99 RTSE12 (1) (1) GUDL1 VBSL GAI15 GAI25 HSB5 HSS5 FOET BPSS1 BRIG5 CONT5 SATN5 HUEC5 CSTD1 CGAIN5 HDEL1 GPSW0 RTSE11 (1) (1) GUDL0 WPOFF GAI14 GAI24 HSB4 HSS4 HTC1 BPSS0 BRIG4 CONT4 SATN4 HUEC4 CSTD0 CGAIN4 HDEL0 HLSEL RTSE10 OLDSB (1) GAI17 GAI27 HSB7 HSS7 AUFD BYPS BRIG7 CONT7 SATN7 HUEC7 CDTO ACGC OFTS1 GPSW1 RTSE13 ADLSB (1) VSTA7 VSTO7 (1) (1) VSTA6 VSTO6 (1) (1) VSTA5 VSTO5 (1) (1) VSTA4 VSTO4 (1) (1) VSTA3 VSTO3 (1) (1) VSTA2 VSTO2 (1) (1) VSTA1 VSTO1 VSTO8 (1) VSTA0 VSTO0 VSTA8 Product specification (1) SAA7113H INTL INTL (1) HLVLN HLCK (1) FIDT FIDT (1) GLIMT GLIMT (1) GLIMB GLIMB (1) WIPA WIPA (1) COPRO SLTCA (1) RDCAP CODE (1) This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1999 Jul 01 50 Philips Semiconductors SUBADDR. (HEX) 40 41 42 to 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 9-bit video input processor REGISTER FUNCTION AC1 LCR2 LCR3 to LCR23 LCR24 FC HOFF VOFF HVOFF For testability Reserved Sliced data identification code SDID Reserved DR (read only) LN1 (read only) LN2 (read only) D7 FISET LCR02_7 LCRN_7 LCR24_7 FC7 HOFF7 VOFF7 FOFF (1) (1) (1) D6 HAM_N LCR02_6 LCRN_6 LCR24_6 FC6 HOFF6 VOFF6 (1) (1) (1) (1) D5 FCE LCR02_5 LCRN_5 LCR24_5 FC5 HOFF5 VOFF5 (1) (1) (1) D4 HUNT_N LCR02_4 LCRN_4 LCR24_4 FC4 HOFF4 VOFF4 VOFF8 (1) (1) D3 (1) D2 CLKSEL1 LCR02_2 LCRN_2 LCR24_2 FC2 HOFF2 VOFF2 HOFF10 (1) (1) D1 CLKSEL0 LCR02_1 LCRN_1 LCR24_1 FC1 HOFF1 VOFF1 HOFF9 (1) (1) D0 (1) LCR02_3 LCRN_3 LCR24_3 FC3 HOFF3 VOFF3 (1) (1) (1) LCR02_0 LCRN_0 LCR24_0 FC0 HOFF0 VOFF0 HOFF8 (1) (1) SDID5 (1) SDID4 (1) SDID3 (1) SDID2 (1) SDID1 (1) SDID0 (1) (1) (1) - - LN3 (1) FC8V - LN2 (1) FC7V F21_N LN1 (1) VPSV LN8 LN0 (1) PPV LN7 DT3 (1) CCV LN6 DT2 (1) - LN5 DT1 (1) - LN4 DT0 (1) Reserved for future extensions 63 to FF Note 1. All unused control bits must be programmed with logic 0 to ensure compatibility to future enhancements. Product specification SAA7113H Philips Semiconductors Product specification 9-bit video input processor 15.2 I2C-bus detail 15.2.2 SUBADDRESS 01H SAA7113H The I2C-bus receiver slave address is 48H/49H. Subaddresses 14H, 18H to 1EH, 20H to 3FH and 63H to FFH are reserved. 15.2.1 SUBADDRESS 00H (READ ONLY REGISTER) Table 26 Horizontal increment delay FUNCTION No update Minimum delay Recommended position IDEL3 IDEL2 IDEL1 IDEL0 1 1 1 0 1 1 0 0 1 1 0 0 1 0 0 0 Table 25 Chip version SA 00 LOGIC LEVELS FUNCTION ID07 Chip Version (CV) CV3 ID06 CV2 ID05 CV1 ID04 CV0 Maximum delay The programming of the horizontal increment delay is used to match internal processing delays to the delay of the ADC. Use recommended position only. 15.2.3 SUBADDRESS 02H Table 27 Analog control 1 SA 02 FUNCTION(1) Mode 0: CVBS (automatic gain) from AI11 (pin 4) Mode 1: CVBS (automatic gain) from AI12 (pin 7) Mode 2: CVBS (automatic gain) from AI21 (pin 43) Mode 3: CVBS (automatic gain) from AI22 (pin 1) Mode 4: reserved Mode 5: reserved Mode 6: Y (automatic gain) from AI11 (pin 4) + C (gain adjustable via GAI28 to GAI20) from AI21 (pin 43); note 2 Mode 7: Y (automatic gain) from AI12 (pin 7) + C (gain adjustable via GAI28 to GAI20) from AI22 (pin 1); note 2 Mode 8: Y (automatic gain) from AI11 (pin 4) + C (gain adapted to Y gain) from AI21 (pin 43); note 2 Mode 9: Y (automatic gain) from AI12 (pin 7) + C (gain adapted to Y gain) from AI22 (pin 1); note 2 Modes 10 to 15: reserved Notes 1. Mode select (see Figs 35 to 42). 2. To take full advantage of the YC-modes 6 to 9 the I2C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1 (full luminance bandwidth). 0 0 0 0 0 0 0 0 1 1 1 CONTROL BITS D3 TO D0 MODE 3 MODE 2 MODE 1 MODE 0 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 1 1999 Jul 01 51 Philips Semiconductors Product specification 9-bit video input processor Table 28 Analog control 1 SA 02, D5 and D4 (see Fig.7) SAA7113H CONTROL BITS D5 AND D4 UPDATE HYSTERESIS FOR 9-BIT GAIN GUDL 1 Off 1 LSB 2 LSB 3 LSB Table 29 Analog control 1 SA 02, D7 and D6 (see Fig.6) CONTROL BITS D7 AND D6 ANALOG FUNCTION SELECT FUSE FUSE 1 Amplifier plus anti-alias filter bypassed Amplifier active Amplifier plus anti-alias filter active 0 0 1 1 FUSE 0 0 1 0 1 0 0 1 1 GUDL 0 0 1 0 1 1999 Jul 01 52 Philips Semiconductors Product specification 9-bit video input processor SAA7113H handbook, halfpage AI22 AI21 AI12 AI11 AD2 handbook, halfpage CHROMA AI22 AI21 AI12 AI11 AD2 CHROMA AD1 LUMA MHB341 AD1 LUMA MHB342 Fig.35 Mode 0; CVBS (automatic gain). Fig.36 Mode 1; CVBS (automatic gain). handbook, halfpage AI22 AI21 AI12 AI11 AD2 handbook, halfpage CHROMA AI22 AI21 AI12 AI11 AD2 CHROMA AD1 LUMA MHB343 AD1 LUMA MHB344 Fig.37 Mode 2; CVBS (automatic gain). Fig.38 Mode 3; CVBS (automatic gain). handbook, halfpage AI22 AI21 AI12 AI11 AD2 handbook, halfpage CHROMA AI22 AI21 AI12 AI11 AD2 CHROMA AD1 LUMA MHB345 AD1 LUMA MHB346 I2C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1 (full luminance bandwidth). I2C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1 (full luminance bandwidth). Fig.39 Mode 6; Y + C (gain channel 2 adjusted via GAI2). Fig.40 Mode 7; Y + C (gain channel 2 adjusted via GAI2). handbook, halfpage AI22 AI21 AI12 AI11 AD2 handbook, halfpage CHROMA AI22 AI21 AI12 AI11 AD2 CHROMA AD1 LUMA MHB347 AD1 LUMA MHB348 I2C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1 (full luminance bandwidth). I2C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1 (full luminance bandwidth). Fig.41 Mode 8; Y + C (gain channel 2 adapted to Y gain). 1999 Jul 01 53 Fig.42 Mode 9; Y + C (gain channel 2 adapted to Y gain). Philips Semiconductors Product specification 9-bit video input processor 15.2.4 SUBADDRESS 03H SAA7113H Table 30 Analog control 2 (AICO2) SA 03 FUNCTION Static gain control channel 1 (GAI18) (see SA 04) Sign bit of gain control Static gain control channel 2 (GAI28) (see SA 05) Sign bit of gain control Gain control fix (GAFIX) Automatic gain controlled by MODE3 to MODE0 Gain is user programmable via GAI1 + GAI2 Automatic gain control integration (HOLDG) AGC active AGC integration hold (freeze) White peak off (WPOFF) White peak control active White peak off AGC hold during vertical blanking period (VBSL) Short vertical blanking (AGC disabled during equalization and serration pulses) Long vertical blanking (AGC disabled from start of pre-equalization pulses until start of active video (line 22 for 60 Hz, line 24 for 50 Hz) HL not reference select (HLNRS) Normal clamping if decoder is in unlocked state Reference select if decoder is in unlocked state 15.2.5 SUBADDRESS 04H 0 1 D6 D6 0 1 D5 D5 0 1 D4 D4 0 1 D3 D3 0 1 D2 D2 see Table 32 D1 see Table 31 D0 LOGIC LEVEL DATA BIT Table 31 Gain control analog (AICO3); static gain control channel 1 GAI1 SA 04, D7 to D0 DECIMAL VALUE 0... ...117... ...511 GAIN (dB) -3 0 6 SIGN BIT GAI18 0 0 1 GAI17 0 0 1 GAI16 0 1 1 CONTROL BITS D7 TO D0 GAI15 0 1 1 GAI14 0 1 1 GAI13 0 0 1 GAI12 0 1 1 GAI11 0 0 1 GAI10 0 1 1 1999 Jul 01 54 Philips Semiconductors Product specification 9-bit video input processor 15.2.6 SUBADDRESS 05H SAA7113H Table 32 Gain control analog (AICO4); static gain control channel 2 GAI2 SA 05, D7 to D0 DECIMAL VALUE 0... ...117... ...511 15.2.7 GAIN (dB) -3 0 6 SIGN BIT (SA 03, D1) GAI28 0 0 1 GAI27 0 0 1 GAI26 0 1 1 CONTROL BITS D7 TO D0 GAI25 0 1 1 GAI24 0 1 1 GAI23 0 0 1 GAI22 0 1 1 GAI21 0 0 1 GAI20 0 1 1 SUBADDRESS 06H Table 33 Horizontal sync begin SA 06, D7 to D0 DELAY TIME (STEP SIZE = 8/LLC) -128...-109 (50 Hz) -128...-108 (60 Hz) -108 (50 Hz)... -107 (60 Hz)... ...108 (50 Hz) ...107 (60 Hz) 109...127 (50 Hz) 108...127 (60 Hz) Recommended value for raw data type; see Fig.24 15.2.8 SUBADDRESS 07H 1 1 1 1 0 0 0 0 1 1 CONTROL BITS D7 TO D0 HSB7 HSB6 HSB5 HSB4 HSB3 HSB2 HSB1 HSB0 forbidden (outside available central counter range) 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 1 0 1 forbidden (outside available central counter range) 1 0 1 0 0 1 Table 34 Horizontal sync stop SA 07, D7 to D0 DELAY TIME (STEP SIZE = 8/LLC) -128...-109 (50 Hz) -128...-108 (60 Hz) -108 (50 Hz)... -107 (60 Hz)... ...108 (50 Hz) ...107 (60 Hz) 109...127 (50 Hz) 108...127 (60 Hz) Recommended value for raw data type; see Fig.24 0 0 1 1 0 0 0 0 1 1 CONTROL BITS D7 TO D0 HSS7 HSS6 HSS5 HSS4 HSS3 HSS2 HSS1 HSS0 forbidden (outside available central counter range) 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 1 0 1 forbidden (outside available central counter range) 0 0 1 1 0 1 1999 Jul 01 55 Philips Semiconductors Product specification 9-bit video input processor 15.2.9 SUBADDRESS 08H SAA7113H Table 35 Sync control SA 08, D7 to D5, D3 to D0 FUNCTION Vertical noise reduction (VNOI) Normal mode (recommended setting) Fast mode [applicable for stable sources only; automatic field detection (AUFD) must be disabled] Free running mode Vertical noise reduction bypassed Horizontal PLL (HPLL) PLL closed PLL open; horizontal frequency fixed Horizontal time constant selection (HTC1 and HTC0) TV mode (recommended for poor quality TV signals only; do not use for new applications) VTR mode (recommended if a deflection control circuit is directly connected to SAA7113H) Reserved Fast locking mode (recommended setting) Forced ODD/EVEN toggle FOET ODD/EVEN signal toggles only with interlaced source ODD/EVEN signal toggles fieldwise even if source is non-interlaced Field selection (FSEL) 50 Hz, 625 lines 60 Hz, 525 lines Automatic field detection (AUFD) Field state directly controlled via FSEL Automatic field detection AUFD AUFD 0 1 D7 D7 FSEL FSEL 0 1 D6 D6 FOET FOET 0 1 D5 D5 HTC1 and HTC0 HTC1 and HTC0 HTC1 and HTC0 HTC1 and HTC0 00 01 10 11 D4 and D3 D4 and D3 D4 and D3 D4 and D3 HPLL HPLL 0 1 D2 D2 VNOI1 VNOI0 VNOI1 VNOI0 VNOI1 VNOI0 VNOI1 VNOI0 0 0 0 1 1 0 1 1 D1 D0 D1 D0 D1 D0 D1 D0 CONTROL BIT LOGIC LEVEL DATA BIT 1999 Jul 01 56 Philips Semiconductors Product specification 9-bit video input processor 15.2.10 SUBADDRESS 09H Table 36 Luminance control SA 09, D7 to D0 FUNCTION Aperture factor (APER); see Figs 12 to 17 Aperture factor = 0 Aperture factor = 0.25 Aperture factor = 0.5 Aperture factor = 1.0 Update time interval for analog AGC value (UPTCV) Horizontal update (once per line) Vertical update (once per field) Vertical blanking luminance bypass (VBLB) Active luminance processing Chrominance trap and peaking stage are disabled during VBI lines determined by VREF = 0; see Table 45 Aperture band-pass (centre frequency) (BPSS) Centre frequency = 4.1 MHz Centre frequency = 3.8 MHz; note 1 Centre frequency = 2.6 MHz; note 1 Centre frequency = 2.9 MHz; note 1 Prefilter active (PREF); see Figs 12 to 17 Bypassed Active Chrominance trap bypass (BYPS) Chrominance trap active; default for CVBS mode Chrominance trap bypassed; default for S-video mode Note 1. Not to be used with bypassed chrominance trap. BYPS BYPS 0 1 PREF PREF 0 1 BPSS1 BPSS0 BPSS1 BPSS0 BPSS1 BPSS0 BPSS1 BPSS0 0 0 0 1 1 0 1 1 VBLB VBLB 0 1 UPTCV UPTCV 0 1 APER1 APER0 APER1 APER0 APER1 APER0 APER1 APER0 0 0 0 1 1 0 1 1 APER/BPSS BIT LOGIC LEVEL SAA7113H DATA BIT D1 D0 D1 D0 D1 D0 D1 D0 D2 D2 D3 D3 D5 D4 D5 D4 D5 D4 D5 D4 D6 D6 D7 D7 1999 Jul 01 57 Philips Semiconductors Product specification 9-bit video input processor 15.2.11 SUBADDRESS 0AH Table 37 Luminance brightness control BRIG7 to BRIG0 SA 0A CONTROL BITS D7 TO D0 OFFSET BRIG7 255 (bright) 128 (CCIR level) 0 (dark) 15.2.12 SUBADDRESS 0BH Table 38 Luminance contrast control CONT7 to CONT0 SA 0B CONTROL BITS D7 TO D0 GAIN CONT7 1.999 (maximum) 1.109 (CCIR level) 1.0 0 (luminance off) -1 (inverse luminance) -2 (inverse luminance) 15.2.13 SUBADDRESS 0CH Table 39 Chrominance saturation control SATN7 to SATN0 SA 0C CONTROL BITS D7 TO D0 GAIN SATN7 1.999 (maximum) 1.0 (CCIR level) 0 (colour off) -1 (inverse chrominance) -2 (inverse chrominance) 15.2.14 SUBADDRESS 0DH Table 40 Chrominance hue control HUEC7 to HUEC0 SA 0D CONTROL BITS D7 TO D0 HUE PHASE (DEG) HUEC7 +178.6... ...0... ...-180 0 0 1 HUEC6 1 0 0 HUEC5 1 0 0 HUEC4 1 0 0 HUEC3 1 0 0 HUEC2 1 0 0 0 0 0 1 1 SATN6 1 1 0 1 0 SATN5 1 0 0 0 0 SATN4 1 0 0 0 0 SATN3 1 0 0 0 0 SATN2 1 0 0 0 0 0 0 0 0 1 1 CONT6 1 1 1 0 1 0 CONT5 1 0 0 0 0 0 CONT4 1 0 0 0 0 0 CONT3 1 0 0 0 0 0 CONT2 1 1 0 0 0 0 1 1 0 BRIG6 1 0 0 BRIG5 1 0 0 BRIG4 1 0 0 BRIG3 1 0 0 BRIG2 1 0 0 SAA7113H BRIG1 1 0 0 BRIG0 1 0 0 CONT1 1 1 0 0 0 0 CONT0 1 1 0 0 0 0 SATN1 1 0 0 0 0 SATN0 1 0 0 0 0 HUEC1 1 0 0 HUEC0 1 0 0 1999 Jul 01 58 Philips Semiconductors Product specification 9-bit video input processor 15.2.15 SUBADDRESS 0EH Table 41 Chrominance control SA 0E FUNCTION 50 Hz 60 Hz CHBW/CSTD BIT LOGIC LEVEL SAA7113H DATA BIT Chrominance bandwidth (CHBW0 and CHBW1) Small bandwidth ( 620 kHz) Nominal bandwidth ( 800 kHz) Medium bandwidth ( 920 kHz) Wide bandwidth ( 1000 kHz) Fast colour time constant (FCTC) Nominal time constant Fast time constant Disable chrominance comb filter (DCCF) Chrominance comb filter on (during lines determined by VREF = 1; see Table 45) Chrominance comb filter permanently off DCCF DCCF 0 1 D3 D3 FCTC FCTC 0 1 D2 D2 CHBW1 CHBW0 CHBW1 CHBW0 CHBW1 CHBW0 CHBW1 CHBW0 0 0 0 1 1 0 1 1 D1 D0 D1 D0 D1 D0 D1 D0 Colour standard selection (CSTD0 to CSTD2); logic levels 100, 110 and 111 are reserved, do not use PAL BGHIN NTSC M (or NTSC-Japan with special level adjustment: brightness subaddress 0AH = 95H; contrast subaddress 0BH = 48H) PAL 4.43 (60 Hz) CSTD2 CSTD1 CSTD0 CSTD2 CSTD1 CSTD0 Combination-PAL N NTSC 4.43 (60 Hz) CSTD2 CSTD1 CSTD0 NTSC N PAL M CSTD2 CSTD1 CSTD0 SECAM reserved CSTD2 CSTD1 CSTD0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 1 D6 D5 D4 D6 D5 D4 D6 D5 D4 D6 D5 D4 D6 D5 D4 NTSC 4.43 (50 Hz) 1999 Jul 01 59 Philips Semiconductors Product specification 9-bit video input processor SAA7113H FUNCTION 50 Hz Clear DTO (CDTO) Disabled Every time CDTO is set, the internal subcarrier DTO phase is reset to 0 and the RTCO output generates a logic 0 at time slot 68 (see external document "RTC Functional Description", available on request). So an identical subcarrier phase can be generated by an external device (e.g. an encoder). 15.2.16 SUBADDRESS 0FH Table 42 Chrominance gain control SA 0F (D6 to D0) CHROMINANCE GAIN VALUE (IF ACGC IS SET TO LOGIC 1) Minimum gain (0.5) Nominal gain (1.125) Maximum gain (7.5) 60 Hz CHBW/CSTD BIT LOGIC LEVEL DATA BIT CDTO CDTO 0 1 D7 D7 CONTROL BITS D6 TO D0 CGAIN6 0 0 1 CGAIN5 0 1 1 CGAIN4 0 0 1 CGAIN3 0 0 1 CGAIN2 0 1 1 CGAIN1 0 0 1 CGAIN0 0 0 1 Table 43 Chrominance gain control SA 0F (D7) D7 AUTOMATIC CHROMINANCE GAIN CONTROL ACGC ACGC On Programmable gain via CGAIN6 to CGAIN0 15.2.17 SUBADDRESS 10H Table 44 Format/delay control SA 10 (D2 to D0) LUMINANCE DELAY COMPENSATION (STEPS IN 2/LLC) -4... ...0... ...3 CONTROL BITS D2 TO D0 YDEL2 1 0 0 YDEL1 0 0 1 YDEL0 0 0 1 0 1 1999 Jul 01 60 Philips Semiconductors Product specification 9-bit video input processor Table 45 VREF pulse position and length VRLN SA 10 (D3) VREF AT 60 Hz 525 LINES VRLN 0 Length Line number Field 1(1) Field 2(1) Note 1. The numbers given in parenthesis refer to ITU line counting. Table 46 Fine position of HS HDEL0 and HDEL1 SA 10 (D5 and D4) CONTROL BITS D5 AND D4 FINE POSITION OF HS (STEPS IN 2/LLC) HDEL1 0 1 2 3 0 0 1 1 first 19 (22) 282 (285) 240 last 258 (261) 521 (524) first 18 (21) 281 (284) 1 242 last 259 (262) 522 (525) first 24 337 0 286 last 309 622 SAA7113H VREF AT 50 Hz 625 LINES 1 288 first 23 336 last 310 623 HDEL0 0 1 0 1 Table 47 Output format selection OFTS0 and OFTS1 SA 10 (D7 and D6); see Tables 6 and 7 V-FLAG GENERATION IN SAV/EAV-CODES Standard ITU 656-format V-flag in SAV/EAV is generated by VREF V-flag in SAV/EAV is generated by data-type Reserved CONTROL BITS D7 AND D6 OFTS1 0 0 1 1 OFTS0 0 1 0 1 1999 Jul 01 61 Philips Semiconductors Product specification 9-bit video input processor 15.2.18 SUBADDRESS 11H Table 48 Output control 1 SA 11 FUNCTION Colour on (COLO) Automatic colour killer Colour forced on YUV decoder bypassed (VIPB) Processed data to VPO output ADC data to VPO output; dependent on mode settings Output enable real-time (OERT) RTS0, RTS1, RTCO high-impedance inputs RTS0, RTCO active, RTS1 active, if RTSE13 to RTSE10 = 0000 Output enable YUV data (OEYC) VPO-bus high-impedance Output VPO-bus active or controlled by RTS1; see Table 19 Selection of horizontal lock indicator for RTS0, RTS1 outputs Standard horizontal lock indicator (low-passed) Fast lock indicator (use is recommended only for high performance input signals) HLSEL HLSEL 0 1 OEYC OEYC 0 1 OERT OERT 0 1 VIPB VIPB 0 1 COLO COLO 0 1 BIT SAA7113H LOGIC LEVEL DATA BIT D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 General purpose switch [available on pin RTS0, if control byte RTSE03 to RTSE00 (subaddress 12H) is set to 0010] LOW HIGH CM99 compatibility to SAA7199 (CM99) Default value To be set only if SAA7199 (digital encoder) is used for re-encoding in conjunction with RTCO CM99 CM99 0 1 D6 D6 GPSW0 GPSW0 0 1 D5 D5 General purpose switch [available on pin RTS1, if control byte RTS103 to RTS100 (subaddress 12H) is set to 0010] LOW HIGH GPSW1 GPSW1 0 1 D7 D7 1999 Jul 01 62 Philips Semiconductors Product specification 9-bit video input processor 15.2.19 SUBADDRESS 12H Table 49 RTS0 output control SA 12 SAA7113H D3 TO D0 RTS0 OUTPUT CONTROL RTSE03 RTSE02 RTSE01 RTSE00 Reserved VIPB (subaddress 11H bit 1) = 0: reserved VIPB (subaddress 11H bit 1) = 1: LSBs of the 9-bit ADCs GPSW0 level (subaddress 11H, bit 5) HL (horizontal lock indicator); selectable via HLSEL (subaddress 11H, bit 4) HSEL = 0: standard horizontal lock indicator HSEL = 1: fast horizontal lock indicator (use is not recommended for sources with unstable timebase e.g. VCRs) VL (vertical and horizontal lock) DL (vertical and horizontal lock and colour detected) PLIN (PAL/SECAM sequence; LOW: PAL/DR line is present) HREF_HS, horizontal reference signal: indicates valid data on the VPO-bus. The positive slope marks the beginning of a new active line. The pulse width is dependent on the data type selected by the control registers LCR2 to LCR24 (subaddress 41H to 57H; see Tables 4 and 61) data type 0 to 6 8 to 15: HIGH period 1440 LLC-cycles (720 samples; see Fig.28) data type 7 (upsampled raw data): HIGH period programmable in LLC8 steps via HSB7 to HSB0, HSS7 to HSS0 (subaddress 06H and 07H), fine position adjustment via HDEL1 to HDEL0 (subaddress 10H, bits 5 and 4) HS, programmable width in LLC8 steps via HSB7 to HSB0 and HSS7 to HSS0 (subaddress 06H and 07H), fine position adjustment in LLC2 steps via HDEL1 to HDEL0 (subaddress 10H, bits 5 and 4) HQ (HREF gated with VREF) ODD, field identifier; HIGH = odd field; see vertical timing diagrams Figs 29 and 30 VS (vertical sync; see vertical timing diagrams Figs 29 and 30) V123 (vertical pulse; see vertical timing diagrams Figs 29 and 30) VGATE (programmable via VSTA8 to VSTA0 and VSTO8 to VSTO0, subaddresses 15H, 16H and 17H) VREF (programmable in two positions via VRLN, subaddress 10H, bit 3) FID (position and polarity programmable via VSTA8 to VSTA0, subaddresses 15H and 17H and FIDP, subaddress 13H bit 3) 1 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 1999 Jul 01 63 Philips Semiconductors Product specification 9-bit video input processor Table 50 RTS1 output control SA 12 SAA7113H D7 TO D4 RTS1 OUTPUT CONTROL RTSE13 RTSE12 RTSE11 RTSE10 3-state, pin RTS1 is used as DOT input; see Table 19 VIPB (subaddress 11H bit 1) = 0: reserved VIPB (subaddress 11H bit 1) = 1: LSBs of the 9-bit ADCs GPSW1 HL (horizontal lock indicator); selectable via HLSEL (subaddress 11H, bit 4) HLSEL = 0: standard horizontal lock indicator HLSEL = 1: fast horizontal lock indicator (use is not recommended for sources with unstable timebase e. g. VCRs) VL (vertical and horizontal lock) DL (vertical and horizontal lock and colour detected) PLIN (PAL/SECAM sequence; LOW: PAL/DR line is present) HREF_HS, horizontal reference signal: indicates valid data on the VPO-bus. The positive slope marks the beginning of a new active line. The pulse width is dependent on the data type selected by the control registers LCR2 to LCR24 (subaddress 41H to 57H; see Tables 4 and 61) data type 0 to 6, 8 to 15: HIGH period 1440 LLC-cycles (720 samples; see Fig.28) data type 7 (upsampled raw data): HIGH period programmable in LLC8 steps via HSB7 to HSB0, HSS7 to HSS0 (subaddress 06H and 07H), fine position adjustment via HDEL1 to HDEL0 (subaddress 10H, bits 5 and 4) HS, programmable width in LLC8 steps via HSB7 to HSB0 and HSS7 to HSS0 (subaddress 06H and 07H), fine position adjustment in LLC2 steps via HDEL1 to HDEL0 (subaddress 10H, bits 5 and 4) HQ (HREF gated with VREF) ODD, field identifier; HIGH = odd field; see vertical timing diagrams Figs 29 and 30 VS (vertical sync); see vertical timing diagrams Figs 29 and 30 V123 (vertical pulse); see vertical timing diagrams Figs 29 and 30 VGATE (programmable via VSTA8 to VSTA0 and VSTO8 to VSTO0, subaddresses 15H, 16H and 17H) VREF (programmable in two positions via VRLN, subaddress 10H, bit 3) FID (position and polarity programmable via VSTA 8 to VSTA0, subaddresses 15H and 17H and FIDP, subaddress 13 bit 3) 1 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 1999 Jul 01 64 Philips Semiconductors Product specification 9-bit video input processor 15.2.20 SUBADDRESS 13H Table 51 Output control SA 13, D7, D4, D3, D1 and D0 FUNCTION Analog test select (AOSL) AOUT connected to internal test point 1 AOUT connected to input AD1 AOUT connected to input AD2 AOUT connected to internal test point 2 AOSL1 AOSL0 AOSL1 AOSL0 AOSL1 AOSL0 AOSL1 AOSL0 0 0 0 1 1 0 1 1 BIT LOGIC LEVEL SAA7113H DATA BIT D1 D0 D1 D0 D1 D0 D1 D0 Field ID polarity if selected on RTS1 or RTS0 outputs if RTSE1, RTSE0 (subaddress 12H) are set to 1111 Default Inverted Selection bit for status byte functionality OLDSB Default status information; see Table 55 Old status information, for compatibility reasons; see Table 55 OLDSB OLDSB 0 1 D4 D4 FIDP FIDP 0 1 D3 D3 Analog-to-digital converter output bits on VPO7 to VPO0 in bypass mode (VIPB = 1, used for test purposes) ADLSB; note 1 AD8 to AD1 (MSBs) on VPO7 to VPO0 AD7 to AD0 (LSBs) on VPO7 to VPO0 Note 1. Analog-to-digital converter selection via MODE3 to MODE0 (subaddress 02H; see Figs 35 to 38). ADLSB ADLSB 0 1 D7 D7 1999 Jul 01 65 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1999 Jul 01 66 Philips Semiconductors 15.2.21 SUBADDRESS 15H 9-bit video input processor Table 52 Start of VGATE pulse (01-transition) and polarity change of FID pulse MSB (SA 17, D0) VSTA8 50 Hz 1st 2nd 1st 2nd 1st 2nd 60 Hz 1st 2nd 1st 2nd 1st 2nd 1 314 2 315 312 625 4 267 5 268 265 3 ...260 1 0 0 0 0 0 1 0 1 0... 0 0 0 0 0 0 0 0 0 262 1 0 0 0 0 0 1 1 0 ...310 1 0 0 1 1 0 1 1 1 0... 0 0 0 0 0 0 0 0 0 312 1 CONTROL BITS D7 TO D0 VSTA7 VSTA6 VSTA5 VSTA4 VSTA3 VSTA2 VSTA1 VSTA0 0 0 1 1 1 0 0 0 FIELD FRAME LINE COUNTING DECIMAL VALUE Product specification SAA7113H This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1999 Jul 01 67 Philips Semiconductors 15.2.22 SUBADDRESS 16H 9-bit video input processor Table 53 Stop of VGATE pulse (10-transition) FRAME LINE COUNTING 1 314 2 315 312 625 4 267 5 268 265 3 ...260 1 0 0 0 0 0 1 0 1 0... 0 0 0 0 0 0 0 0 0 262 1 0 0 0 0 0 1 1 0 ...310 1 0 0 1 1 0 1 1 1 0... 0 0 0 0 0 0 0 0 0 MSB (SA 17, D0) VSTO8 50 Hz 1st 2nd 1st 2nd 1st 2nd 60 Hz 1st 2nd 1st 2nd 1st 2nd 312 1 CONTROL BITS D7 TO D0 VSTO7 VSTO6 VSTO5 VSTO4 VSTO3 VSTO2 VSTO1 VSTO0 0 0 1 1 1 0 0 0 FIELD DECIMAL VALUE Product specification SAA7113H Philips Semiconductors Product specification 9-bit video input processor 15.2.23 SUBADDRESS 17H Table 54 VGATE MSBs FUNCTION VSTA8, see SA 15 MSB VGATE start VSTO8, see SA 16 MSB VGATE stop 15.2.24 SUBADDRESS 1FH (READ ONLY REGISTER) Table 55 Status byte video decoder SA 1F I2C-BUS CONTROL BIT RDCAP CODE COPRO SLTCA WIPA GLIMB GLIMT FIDT HLVLN HLCK INTL FUNCTION ready for capture (all internal loops locked); active HIGH (OLDSB = 0) see Table 53 see Table 52 LOGIC LEVEL SAA7113H CONTROL BIT D0 D1 DATA BIT D0 colour signal in accordance with selected standard has been detected; active HIGH (OLDSB = 1) copy protected source detected according to macrovision version up to 7.01 (OLDSB = 0) slow time constant active in WIPA mode; active HIGH (OLDSB = 1) white peak loop is activated; active HIGH gain value for active luminance channel is limited [min (bottom)]; active HIGH gain value for active luminance channel is limited [max (top)]; active HIGH identification bit for detected field frequency; LOW = 50 Hz, HIGH = 60 Hz status bit for horizontal/vertical loop: LOW = locked, HIGH = unlocked (OLDSB = 0) status bit for locked horizontal frequency; LOW = locked, HIGH = unlocked (OLDSB = 1) status bit for interlace detection; LOW = non-interlaced, HIGH = interlaced D7 D2 D3 D4 D5 D6 D1 15.2.25 SUBADDRESS 40H Table 56 Data slicer clock selection SLICER SET (40H) AMPLITUDE SEARCHING Reserved 13.5 MHz (default) Reserved Reserved Table 57 Amplitude searching SLICER SET (40H) AMPLITUDE SEARCHING Amplitude searching active (default) Amplitude searching stopped 1999 Jul 01 68 CONTROL BIT D4 HUNT_N 0 1 CONTROL BITS D2 AND D1 CLKSEL1 00 01 10 11 CLKSEL0 Philips Semiconductors Product specification 9-bit video input processor Table 58 Framing code error SLICER SET (40H) FRAMING CODE ERROR One framing code error allowed No framing code errors allowed Table 59 Hamming check SLICER SET (40H) HAMMING CHECK Hamming check for 2 bytes after framing code, dependent on data type (default) No hamming check Table 60 Field size select SLICER SET (40H) FIELD SIZE SELECT 50 Hz field rate 60 Hz field rate CONTROL BIT D7 FISET 0 1 CONTROL BIT D6 HAM_N 0 1 CONTROL BIT D5 FCE 0 1 SAA7113H 1999 Jul 01 69 Philips Semiconductors Product specification 9-bit video input processor 15.2.26 SUBADDRESS 41H TO 57H Table 61 LCR register 2 to 24 (41H to 57H); see Table 4 D7 TO D4 LCR REGISTER 2 TO 24 (41H TO 57H) WST625 CC625 VPS WSS WST525 CC525 Test line Intercast VITC625 Reserved NABTS Japtext JFS teletext EuroWST, CCST European closed caption video programming service wide screen signalling bits US teletext (WST) US closed caption (line 21) video component signal, VBI region oversampled CVBS data VITC/EBU time codes (Europe) VITC/SMPTE time codes (USA) reserved US NABTS MOJI (Japanese) Japanese format switch (L20/22) FRAMING CODE 27H 001 9951H 1E3C1FH 27H 001 - - programmable programmable programmable - - programmable (A7H) programmable - DT3 TO DT0(1) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 SAA7113H D3 TO D0 DT3 TO DT0(1) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 General text teletext Active video video component signal, active video region (default) Note 1. The assignment of the upper and lower nibbles to the corresponding field depends on the setting of FOFF (subaddress 5B, D7); see Table 62. Table 62 Setting of FOFF FOFF 0 1 D7 TO D4 field 1 field 2 D3 TO D0 field 2 field 1 1999 Jul 01 70 Philips Semiconductors Product specification 9-bit video input processor 15.2.27 SUBADDRESS 58H Table 63 Framing code for programmable data types SLICER SET (58H) PROGRAMMABLE FRAMING CODE (Default) 15.2.28 SUBADDRESS 59H Table 64 Horizontal offset SLICER SET (59H, 5BH) HORIZONTAL OFFSET Recommended value 15.2.29 SUBADDRESS 5AH Table 65 Vertical offset SLICER SET (5AH, 5BH) VERTICAL OFFSET Minimum value 0 Maximum value 312 Value for 50 Hz 625 lines input Value for 60 Hz 525 lines input 15.2.30 SUBADDRESS 5BH Table 66 Field offset, MSBs for vertical and horizontal offsets SLICER SET (5BH) FIELD OFFSET No modification of internal field indicator Invert field indicator (even/odd; default) 15.2.31 SUBADDRESS 5EH Table 67 SDID codes SLICER SET (5EH) SDID codes SDID5 to SDID0 = 0H (default) D5 SDID5 0 D4 SDID4 0 D3 SDID3 0 D2 SDID2 0 CONTROL BIT D7 FOFF 0 1 CONTROL BIT 5BH, D4 VOFF8 0 1 0 0 CONTROL BITS ADDRESS 5BH, DATA BITS D2 TO D0 HOFF10 TO HOFF8 3H SAA7113H CONTROL BITS D7 TO D0 FC7 TO FC0 40H CONTROL BITS ADDRESS 59H, DATA BITS D7 TO D0 HOFF7 TO HOFF0 54H CONTROL BITS ADDRESS 5AH, DATA BITS D7 TO D0 VOFF7 TO VOFF0 0H 38H 07H 0AH D1 SDID1 0 D0 SDID0 0 1999 Jul 01 71 Philips Semiconductors Product specification 9-bit video input processor 15.2.32 SUBADDRESS 60H (READ-ONLY REGISTER) Table 68 Slicer status bit (60H) read only SLICER STATUS BIT (60H) READ ONLY CLOSED CAPTION VALID No closed caption in the last frame Closed caption detected Table 69 Slicer status bit (60H) read only SLICER STATUS BIT (60H) READ ONLY PALplus VALID No PALplus in the last frame PALplus detected Table 70 Slicer status bit (60H) read only SLICER STATUS BIT (60H) READ ONLY VPS VALID No VPS in the last frame VPS detected Table 71 Slicer status bit (60H) read only SLICER STATUS BIT (60H) READ ONLY FRAMING CODE VALID No framing code in the last frame Framing code with 1 error detected in the last frame Framing code without errors detected in the last frame Note 1. X = don't care. 15.2.33 SUBADDRESS 61H (READ-ONLY REGISTER) Table 72 Slicer status bits (61H and 62H) read only SLICER STATUS BITS (61H AND 62H) READ ONLY Line number 15.2.34 SUBADDRESS 62H (READ-ONLY REGISTER) Table 73 Slicer status bits (62H) read only SLICER STATUS BITS (62H) READ ONLY Data type according to Table 4 ADDRESS 61H, CONTROL BITS D4 TO D0 LN8 to LN4 CONTROL BIT D4 VPSV 0 1 CONTROL BIT D3 PPV 0 1 CONTROL BIT D2 CCV 0 1 SAA7113H CONTROL BITS D6 AND D5 FC8V 0 0 1 FC7V 0 1 X(1) ADDRESS 62H, CONTROL BITS D7 TO D4 LN3 to LN0 CONTROL BITS D3 TO D0 DT3 to DT0 1999 Jul 01 72 Philips Semiconductors Product specification 9-bit video input processor 16 I2C-BUS START SET-UP The given values force the following behaviour of the SAA7113H: * The analog input AI11 expects a signal in CVBS format; analog anti-alias filter and AGC active * Automatic field detection enabled, PAL BDGHI or NTSC M standard expected * Standard ITU 656 output format enabled, VBI-data slicer disabled; see Table 74 note 2 * Contrast, brightness and saturation control in accordance with ITU standards * Chrominance processing with nominal bandwidth (800 kHz). Table 74 I2C-bus start set-up values SUB (HEX) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 FUNCTION chip version increment delay analog input control 1 analog input control 2 analog input control 3 analog input control 4 horizontal sync start horizontal sync stop sync control luminance control luminance brightness luminance contrast chrominance hue control chrominance control chrominance gain control format/delay control ID07 to ID00 X, X, X, X, IDEL FUSE1 and FUSE0, GUDL1 to GUDL0, MODE3 to MODE0 X, HLNRS, VBSL, WPOFF, HOLDG, GAFIX, GAI28 and GAI18 GAI17 to GAI10 GAI27 to GAI20 HSB7 to HSB0 HSS7 to HSS0 AUFD, FSEL, FOET, HTC1, HTC0, HPLL, VNOI1 and VNOI0 BYPS, PREF, BPSS1 and BPSS0, VBLB, UPTCV, APER1 and APER0 BRIG7 to BRIG0 CONT7 to CONT0 HUEC7 to HUEC0 CDTO, CSTD2 to CSTD0, DCCF, FCTC, CHBW1 and CHBW0 ACGC, CGAIN6 to CGAIN0 OFTS1 and OFTS0, HDEL1 and HDEL0, VRLN, YDEL2 to YDEL0 GPSW1, CM99, GPSW0, HLSEL, OEYC, OERT, VIPB and COLO ADLSB, X, X, OLDSB, FIDP, X, AOSL1 and AOSL0 0 1 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 NAME(1) 7 6 SAA7113H VALUES (BIN) 5 4 3 1 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 2 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 1 1 0 1 0 1 0 0 1 0 0 (HEX) START 08 C0 33 00 00 E9 0D 98 01 80 47 40 00 01 2A 00 read only chrominance saturation SATN7 to SATN0 11 12 13 14 output control 1 output control 2 output control 3 reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0C 01 00 00 RTSE13 to RTSE10, RTSE03 to RTSE00 0 0 0 1999 Jul 01 73 Philips Semiconductors Product specification 9-bit video input processor SAA7113H SUB (HEX) 15 16 17 18 to 1E 1F 20 to 3F 40 41 to 57 58 59 5A 5B FUNCTION VGATE start VGATE stop MSBs for VGATE control reserved decoder status byte reserved slicer control 1 line control register 2 to 24 programmable framing code horizontal offset for slicer vertical offset for slicer field offset and MSBs for horizontal and vertical offset reserved NAME(1) 7 VSTA7 to VSTA0 VSTO7 to VSTO0 X, X, X, X, X, X, VSTO8 and VSTA8 0 0 0 0 INTL, HVLN, FIDT, GLIMT, GLIMB, WIPA, COPRP and RDCAP 0 FISET, HAM_N, FCE and HUNT_N LCRn7 to LCRn0 FC7 to FC0 HOFF7 to HOFF0 VOFF7 to VOFF0 FOFF, X, X, VOFF8, X, HOFF10 to HOFF8 0 1 0 0 0 1 0 0 1 0 1 0 0 6 0 0 0 0 VALUES (BIN) 5 0 0 0 0 4 0 0 0 0 3 0 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 (HEX) START 00 00 00 00 read-only register 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 0 1 1 00 02(2) FF(2) 00 54(2) 07(2) 83(2) 5C and 5D 5E 5F 60 61 62 Notes 0 0 0 0 0 0 0 0 00 sliced data identification code reserved slicer status byte 1 slicer status byte 2 X, X, SDID5 to SDID0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 00 X, FC8V, FC7V, VPSV, PPV, CCV, X, X X, X, F21_N, LN8 to LN4 LN3 to LN0, DT3 to DT0 read-only register read-only register read-only register 1. All X values must be set to LOW. For SECAM decoding set register 0EH to 50H. 2. For proper data slicer programming refer to Tables 8 to 11 and 4. 1999 Jul 01 74 Philips Semiconductors Product specification 9-bit video input processor 17 PACKAGE OUTLINE QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SAA7113H SOT307-2 c y X A 33 34 23 22 ZE e E HE wM bp pin 1 index 44 1 bp D HD wM 11 ZD B vM B vMA 12 detail X A A2 (A 3) Lp L A1 e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.10 A1 0.25 0.05 A2 1.85 1.65 A3 0.25 bp 0.40 0.20 c 0.25 0.14 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.8 HD 12.9 12.3 HE 12.9 12.3 L 1.3 Lp 0.95 0.55 v 0.15 w 0.15 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 10 0o o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT307-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 97-08-01 1999 Jul 01 75 Philips Semiconductors Product specification 9-bit video input processor 18 SOLDERING 18.1 Introduction to soldering surface mount packages SAA7113H * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 18.4 Manual soldering This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. 18.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. 18.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 1999 Jul 01 76 Philips Semiconductors Product specification 9-bit video input processor 18.5 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, SQFP HLQFP, HSQFP, HSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes not suitable not suitable(2) suitable not recommended(3)(4) not recommended(5) suitable suitable suitable suitable suitable SAA7113H REFLOW(1) 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 1999 Jul 01 77 Philips Semiconductors Product specification 9-bit video input processor 19 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values SAA7113H This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 20 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 21 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1999 Jul 01 78 Philips Semiconductors Product specification 9-bit video input processor NOTES SAA7113H 1999 Jul 01 79 Philips Semiconductors - a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 02 67 52 2531, Fax. +39 02 67 52 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 62 5344, Fax.+381 11 63 5777 For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1999 Internet: http://www.semiconductors.philips.com SCA 66 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545006/01/pp80 Date of release: 1999 Jul 01 Document order number: 9397 750 04567 |
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